- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄224114 > LTC2254IUH#TR (LINEAR TECHNOLOGY CORP) 14-Bit, 105Msps Low Power 3V ADCs; Package: QFN; No of Pins: 32; Temperature Range: -40°C to +85°C PDF資料下載
參數(shù)資料
| 型號(hào)： | LTC2254IUH#TR |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | ADC |
| 英文描述： | 14-Bit, 105Msps Low Power 3V ADCs; Package: QFN; No of Pins: 32; Temperature Range: -40°C to +85°C |
| 中文描述： | 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC32 |
| 封裝： | 5 X 5 MM, PLASTIC, MO-220-WHHD, QFN-32 |
| 文件頁數(shù)： | 9/24頁 |
| 文件大?。?/td> | 620K |
| 代理商： | LTC2254IUH#TR |
LTC2255/LTC2254
17
22554fa
APPLICATIO S I FOR ATIO
WU
UU
bearing on how much SNR degradation will be experi-
enced. For high crest factor signals such as WCDMA or
OFDM, where the nominal power level must be at least 6dB
to 8dB below full scale, the use of these translators will
have a lesser impact.
The transformer in the example may be terminated with
the appropriate termination for the signaling in use. The
use of a transformer with a 1:4 impedance ratio may be
desirable in cases where lower voltage differential signals
are considered. The center tap may be bypassed to ground
through a capacitor close to the ADC if the differential
signals originate on a different plane. The use of a capaci-
tor at the input may result in peaking, and depending on
transmission line length may require a 10
to 20 ohm
series resistor to act as both a low pass filter for high
frequency noise that may be induced into the clock line by
neighboring digital signals, as well as a damping mecha-
nism for reflections.
Maximum and Minimum Conversion Rates
The maximum conversion rate for the LTC2255/LTC2254
is 125Msps (LTC2255) and 105Msps (LTC2254). The
lower limit of the LTC2255/LTC2254 sample rate is deter-
mined by droop of the sample-and-hold circuits. The
pipelined architecture of this ADC relies on storing analog
signals on small valued capacitors. Junction leakage will
discharge the capacitors. The specified minimum operat-
ing frequency for the LTC2255/LTC2254 is 1Msps.
Clock Duty Cycle Stabilizer
An optional clock duty cycle stabilizer circuit ensures high
performance even if the input clock has a non
50% duty cycle. Using the clock duty cycle stabilizer is
recommended for most applications. To use the clock
duty cycle stabilizer, the MODE pin should be connected to
1/3VDD or 2/3VDD using external resistors.
This circuit uses the rising edge of the CLK pin to sample
the analog input. The falling edge of CLK is ignored and
the internal falling edge is generated by a phase-locked
loop. The input clock duty cycle can vary from 40% to 60%
and the clock duty cycle stabilizer will maintain a constant
50% internal duty cycle. If the clock is turned off for a
long period of time, the duty cycle stabilizer circuit will
Figure 14. Digital Output Buffer
LTC2255/LTC2254
22554 F14
OVDD
VDD
0.1
F
43
TYPICAL
DATA
OUTPUT
OGND
OVDD
0.5V
TO 3.6V
PREDRIVER
LOGIC
DATA
FROM
LATCH
OE
require a hundred clock cycles for the PLL to lock onto the
input clock.
For applications where the sample rate needs to be changed
quickly, the clock duty cycle stabilizer can be disabled. If
the duty cycle stabilizer is disabled, care should be taken
to make the sampling clock have a 50% (
±5%) duty cycle.
DIGITAL OUTPUTS
Table 1 shows the relationship between the analog input
voltage, the digital data bits, and the overflow bit.
Table 1. Output Codes vs Input Voltage
AIN+ – AIN–
D13 – D0
(2V Range)
OF
(Offset Binary)
(2’s Complement)
>+1.000000V
1
11 1111 1111 1111
01 1111 1111 1111
+0.999878V
0
11 1111 1111 1111
01 1111 1111 1111
+0.999756V
0
11 1111 1111 1110
01 1111 1111 1110
+0.000122V
0
10 0000 0000 0001
00 0000 0000 0001
0.000000V
0
10 0000 0000 0000
00 0000 0000 0000
–0.000122V
0
01 1111 1111 1111
11 1111 1111 1111
–0.000244V
0
01 1111 1111 1110
11 1111 1111 1110
–0.999878V
0
00 0000 0000 0001
10 0000 0000 0001
–1.000000V
0
00 0000 0000 0000
10 0000 0000 0000
<–1.000000V
1
00 0000 0000 0000
10 0000 0000 0000
Digital Output Buffers
Figure 14 shows an equivalent circuit for a single output
buffer. Each buffer is powered by OVDD and OGND, iso-
lated from the ADC power and ground. The additional
N-channel transistor in the output driver allows operation
down to low voltages. The internal resistor in series with
the output makes the output appear as 50
to external
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LTC2255CUH#TR | 14-Bit, 125Msps Low Power 3V ADCs; Package: QFN; No of Pins: 32; Temperature Range: 0°C to +70°C |
| LTC2280CUP | Dual 10-Bit, 105Msps Low Noise 3V ADC; Package: QFN; No of Pins: 64; Temperature Range: 0°C to +70°C |
| LTC2280CUP#TR | Dual 10-Bit, 105Msps Low Noise 3V ADC; Package: QFN; No of Pins: 64; Temperature Range: 0°C to +70°C |
| LTC2280IUP | Dual 10-Bit, 105Msps Low Noise 3V ADC; Package: QFN; No of Pins: 64; Temperature Range: -40°C to +85°C |
| LTC2280IUP#TR | Dual 10-Bit, 105Msps Low Noise 3V ADC; Package: QFN; No of Pins: 64; Temperature Range: -40°C to +85°C |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LTC2255 | 制造商:LINER 制造商全稱:Linear Technology 功能描述:14-Bit, 125/105Msps Low Power 3V ADCs |
| LTC2255CUH | 制造商:Linear Technology 功能描述:ADC Single Pipelined 125Msps 14-bit Parallel 32-Pin QFN EP |
| LTC2255CUH#PBF | 功能描述:IC ADC 14-BIT 125MSPS 3V 32-QFN RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 其它有關(guān)文件:TSA1204 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應(yīng)商設(shè)備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類型:4 個(gè)單端，單極；2 個(gè)差分，單極 產(chǎn)品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6 |
| LTC2255CUH#TRPBF | 功能描述:IC ADC 14BIT 125MSPS 3V 32-QFN RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):12 采樣率（每秒）:3M 數(shù)據(jù)接口:- 轉(zhuǎn)換器數(shù)目:- 功率耗散（最大）:- 電壓電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 供應(yīng)商設(shè)備封裝:SOT-23-6 包裝:帶卷 (TR) 輸入數(shù)目和類型:- |
| LTC2255IUH | 制造商:Linear Technology 功能描述:ADC Single Pipelined 125Msps 14-bit Parallel 32-Pin QFN EP |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。