參數(shù)資料
型號: LTC2231IUP
廠商: LINEAR TECHNOLOGY CORP
元件分類: ADC
英文描述: Electrical Specifications Subject to Change
中文描述: 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64
封裝: 9 X 9 MM, PLASTIC, MO-220-WNJR, QFN-64
文件頁數(shù): 5/28頁
文件大?。?/td> 695K
代理商: LTC2231IUP
LTC2230/LTC2231
5
22301p
POWER REQUIREW
range, otherwise specifications are at T
A
= 25
°
C. (Note 9)
U
TIW
range, otherwise specifications are at T
A
= 25
°
C. (Note 4)
The
denotes the specifications which apply over the full operating temperature
LTC2230
TYP
3.3
2
35
LTC2231
TYP
3.3
2
35
SYMBOL
V
DD
P
SHDN
P
NAP
LVDS OUTPUT MODE
OV
DD
I
VDD
I
OVDD
P
DISS
CMOS OUTPUT MODE
OV
DD
I
VDD
P
DISS
PARAMETER
Analog Supply Voltage
Shutdown Power
Nap Mode Power
CONDITIONS
MIN
3.1
MAX
3.5
MIN
3.1
MAX
3.5
UNITS
V
SHDN = H, OE = H, No CLK
SHDN = H, OE = L, No CLK
mW
mW
Output Supply Voltage
Analog Supply Current
Output Supply Current
Power Dissipation
3
3.3
264
55
1050
3.6
290
61
1160
3
3.3
196
55
828
3.6
216
61
915
V
mA
mA
mW
Output Supply Voltage
Analog Supply Current
Power Dissipation
0.5
3.3
264
890
3.6
290
0.5
3.3
196
660
3.6
216
V
mA
mW
LTC2230
TYP
LTC2231
TYP
SYMBOL
f
S
t
L
PARAMETER
Sampling Frequency
ENC Low Time
CONDITIONS
MIN
1
2.8
2
2.8
2
MAX
170
500
500
500
500
MIN
1
3.5
2
3.5
2
MAX
135
500
500
500
500
UNITS
MHz
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
2.94
2.94
2.94
2.94
0
5
3.7
3.7
3.7
3.7
0
5
ns
ns
ns
ns
ns
ns
t
H
ENC High Time
t
AP
t
OE
LVDS OUTPUT MODE
t
D
t
C
Sample-and-Hold Aperture Delay
Output Enable Delay
(Note 7)
10
10
ENC to DATA Delay
ENC to CLOCKOUT Delay
DATA to CLOCKOUT Skew
Rise Time
Fall Time
Pipeline Latency
(Note 7)
(Note 7)
(t
C
- t
D
) (Note 7)
1.3
1.3
–0.6
2.2
2.2
0
0.5
0.5
5
3.5
3.5
0.6
1.3
1.3
–0.6
2.2
2.2
0
0.5
0.5
5
3.5
3.5
0.6
ns
ns
ns
ns
ns
Cycles
CMOS OUTPUT MODE
t
D
t
C
ENC to DATA Delay
ENC to CLOCKOUT Delay
DATA to CLOCKOUT Skew
(Note 7)
(Note 7)
(t
C
- t
D
) (Note 7)
1.3
1.3
–0.6
2.1
2.1
0
5
5
3.5
3.5
0.6
1.3
1.3
–0.6
2.1
2.1
0
5
5
3.5
3.5
0.6
ns
ns
ns
Pipeline Latency Full Rate CMOS
Cycles
Cycles
Cycles
Demuxed Interleaved
Demuxed Simultaneous
5 and 6
5 and 6
The
denotes the specifications which apply over the full operating temperature
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