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參數(shù)資料
| 型號： | LTC2230CUP |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | ADC |
| 英文描述： | Electrical Specifications Subject to Change |
| 中文描述： | 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64 |
| 封裝： | 9 X 9 MM, PLASTIC, MO-220-WNJR, QFN-64 |
| 文件頁數(shù)： | 22/28頁 |
| 文件大?。?/td> | 695K |
| 代理商： | LTC2230CUP |
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LTC2230/LTC2231
22
22301p
Digital Output Buffers (LVDS Mode)
Figure 13b shows an equivalent circuit for a differential
output pair in the LVDS output mode. A 3.5mA current is
steered from OUT
+
to OUT
–
or vice versa which creates a
±
350mV differential voltage across the 100
termination
resistor at the LVDS receiver. A feedback loop regulates
the common mode output voltage to 1.25V. For proper
operation each LVDS output pair needs an external 100
termination resistor, even if the signal is not used (such as
OF
+
/OF
–
or CLKOUT
+
/CLKOUT
–
). To minimize noise the
PC board traces for each LVDS output pair should be
routed close together. To minimize clock skew all LVDS PC
board traces should have about the same length.
APPLICATIOU
W
U
U
Overflow Bit
An overflow output bit indicates when the converter is
overranged or underranged. In CMOS mode, a logic high
on the OFA pin indicates an overflow or underflow on the
A data bus, while a logic high on the OFB pin indicates an
overflow or underflow on the B data bus. In LVDS mode,
a differential logic high on the OF
+
/OF
–
pins indicates an
overflow or underflow.
Output Clock
The ADC has a delayed version of the ENC
+
input available
as a digital output, CLKOUT. The CLKOUT pin can be used
to synchronize the converter data to the digital system. This
is necessary when using a sinusoidal encode. In all CMOS
modes, A bus data will be updated just after CLKOUTA rises
and can be latched on the falling edge of CLKOUTA. In demux
CMOS mode with interleaved update, B bus data will be
updated just after CLKOUTB rises and can be latched on the
falling edge of CLKOUTB. In demux CMOS mode with si-
multaneous update, B bus data will be updated just after
CLKOUTB falls and can be latched on the rising edge of
CLKOUTB. In LVDS mode, data will be updated just after
CLKOUT
+
/CLKOUT
–
rises and can be latched on the falling
edge of CLKOUT
+
/CLKOUT
–
.
Output Driver Power
Separate output power and ground pins allow the output
drivers to be isolated from the analog circuitry. The power
supply for the digital output buffers, OV
DD
, should be tied
to the same power supply as for the logic being driven. For
example if the converter is driving a DSP powered by a 1.8V
supply then OV
DD
should be tied to that same 1.8V supply.
In the CMOS output mode, OV
DD
can be powered with any
voltage up to the V
DD
of the part. OGND can be powered with
any voltage from GND up to 1V and must be less than OV
DD
.
The logic outputs will swing between OGND and OV
DD
.
In the LVDS output mode, OV
DD
should be connected to a
3.3V supply and OGND should be connected to GND.
Output Enable
The outputs may be disabled with the output enable pin, OE.
In CMOS or LVDS output modes OE high disables all data
outputs including OF and CLKOUT. The data access and bus
LTC2230/LTC2231
22301 F13b
OV
DD
LVDS
RECEIVER
OGND
1.25V
D
D
D
D
OUT
+
OUT
–
100
+
–
3.5mA
10k
10k
Figure 13b. Digital Output in LVDS Mode
Table 2. MODE Pin Function
Clock Duty
Cycle Stablizer
Off
On
On
Off
MODE Pin
0
1/3V
DD
2/3V
DD
V
DD
Output Format
Straight Binary
Straight Binary
2’s Complement
2’s Complement
Data Format
The LTC2230/LTC2231 parallel digital output can be se-
lected for offset binary or 2’s complement format. The
format is selected with the MODE pin. Connecting MODE
to GND or 1/3V
DD
selects straight binary output format.
Connecting MODE to 2/3V
DD
or V
DD
selects 2’s comple-
ment output format. An external resistor divider can be
used to set the 1/3V
DD
or 2/3V
DD
logic values. Table 2
shows the logic states for the MODE pin.
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