參數(shù)資料
型號(hào)： LTC2230CUP
廠商： LINEAR TECHNOLOGY CORP
元件分類： ADC
英文描述： Electrical Specifications Subject to Change
中文描述： 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64
封裝： 9 X 9 MM, PLASTIC, MO-220-WNJR, QFN-64
文件頁數(shù)： 12/28頁
文件大?。?/td> 695K
代理商： LTC2230CUP
LTC2230/LTC2231
12
22301p
(CMOS Mode)
A
IN+
(Pins 1, 2):
Positive Differential Analog Input.
A
IN–
(Pins 3, 4):
Negative Differential Analog Input.
REFHA (Pins 5, 6):
ADC High Reference. Bypass to
Pins 7, 8 with 0.1
μ
F ceramic chip capacitor, to Pins 11, 12
with a 2.2
μ
F ceramic capacitor and to ground with 1
μ
F
ceramic capacitor.
REFLB (Pins 7, 8):
ADC Low Reference. Bypass to Pins 5,
6 with 0.1
μ
F ceramic chip capacitor. Do not connect to
Pins 11, 12.
REFHB (Pins 9, 10):
ADC High Reference. Bypass to
Pins 11, 12 with 0.1
μ
F ceramic chip capacitor. Do not
connect to Pins 5, 6.
REFLA (Pins 11, 12):
ADC Low Reference. Bypass to
Pins 9, 10 with 0.1
μ
F ceramic chip capacitor, to Pins 5, 6
with a 2.2
μ
F ceramic capacitor and to ground with 1
μ
F
ceramic capacitor.
V
DD
(Pins 13, 14, 15, 62, 63):
3.3V Supply. Bypass to
GND with 0.1
μ
F ceramic chip capacitors.
GND (Pins 16, 61, 64):
ADC Power Ground.
ENC
+
(Pin 17):
Encode Input. The input sample starts on
the positive edge.
ENC
–
(Pin 18):
Encode Complement Input. Conversion
starts on the negative edge. Bypass to ground with 0.1
μ
F
ceramic for single-ended ENCODE signal.
SHDN (Pin 19):
Shutdown Mode Selection Pin. Connect-
ing SHDN to GND and OE to GND results in normal
operation with the outputs enabled. Connecting SHDN to
GND and OE to V
DD
results in normal operation with the
outputs at high impedance. Connecting SHDN to V
DD
and
OE to GND results in nap mode with the outputs at high
impedance. Connecting SHDN to V
DD
and OE to V
DD
results in sleep mode with the outputs at high impedance.
OE (Pin 20):
Output Enable Pin. Refer to SHDN pin
function.
DNC (Pins 21, 22, 40, 43):
Do not connect these pins.
DB0 - DB9 (Pins 23, 24, 27, 28, 29, 30, 31, 32, 35, 36):
Digital Outputs, B bus. At high impedance in full rate
CMOS mode. DB9 is MSB.
OGND (Pins 25, 33, 41, 50):
Output Driver Ground.
OV
DD
(Pins 26, 34, 42, 49):
Positive Supply for the Output
Drivers. Bypass to ground with 0.1
μ
F ceramic chip
capacitor.
OFB (Pin 37):
Over/Under Flow Output for B bus. High
when an over or under flow has occurred. At high imped-
ance in full rate CMOS mode.
CLKOUTB (Pin 38):
Data Valid Output for B bus. In demux
mode with interleaved update, latch B bus data on the
falling edge of CLKOUTB. In demux mode with simulta-
neous update, latch B bus data on the rising edge of
CLKOUTB. This pin does not become high impedance in
full rate CMOS mode.
CLKOUTA (Pin 39):
Data Valid Output for A bus. Latch A
bus data on the falling edge of CLKOUTA.
DA0 - DA9 (Pins 44 to 48, 51 to 55):
Digital Outputs, A bus.
DA9 is the MSB.
OFA (Pin 56):
Over/Under Flow Output for A bus. High
when an over or under flow has occurred.
LVDS (Pin 57):
Output Mode Selection Pin. Connecting
LVDS to 0V selects full rate CMOS mode. Connecting
LVDS to 1/3V
DD
selects demux CMOS mode with simulta-
neous update. Connecting LVDS to 2/3V
DD
selects demux
CMOS mode with interleaved update. Connecting LVDS to
V
DD
selects LVDS mode.
MODE (Pin 58):
Output Format and Clock Duty Cycle
Stabilizer Selection Pin. Connecting MODE to 0V selects
straight binary output format and turns the clock duty
cycle stabilizer off. Connecting MODE to 1/3V
DD
selects
straight binary output format and turns the clock duty
cycle stabilizer on. Connecting MODE to 2/3V
DD
selects
2’s complement output format and turns the clock duty
cycle stabilizer on. Connecting MODE to V
DD
selects 2’s
complement output format and turns the clock duty cycle
stabilizer off.
PIU
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