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參數(shù)資料
| 型號(hào)： | LTC2226HLU |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | ADC |
| 英文描述： | 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP32 |
| 封裝： | 5 X 5 MM, PLASTIC, MS-026, TQFP-32 |
| 文件頁數(shù)： | 14/16頁 |
| 文件大?。?/td> | 679K |
| 代理商： | LTC2226HLU |
LTC2226H
2226hfa
pin FuncTions
AIN+ (Pin 1): Positive Differential Analog Input.
AIN- (Pin 2): Negative Differential Analog Input.
GND (Pins 3, 6, 8): ADC Power Ground.
REFH (Pin 4): ADC High Reference. Bypass to pin 5 with
a 0.1F ceramic chip capacitor as close to the pin as
possible. Also bypass to pin 5 with an additional 2.2F
ceramic chip capacitor and to GND with a 1F ceramic
chip capacitor.
REFL (Pin 5): ADC Low Reference. Bypass to pin 4 with
a 0.1F ceramic chip capacitor as close to the pin as
possible. Also bypass to pin 4 with an additional 2.2F
ceramic chip capacitor and to ground with a 1F ceramic
chip capacitor.
VDD (Pins 7, 32): 3V Supply. Bypass to GND with 0.1F
ceramic chip capacitors.
CLK (Pin 9): Clock Input. The input sample starts on the
positive edge.
SHDN(Pin10):ShutdownModeSelectionPin.Connecting
SHDN to GND and OE to GND results in normal operation
with the outputs enabled. Connecting SHDN to GND and
OE to VDD results in normal operation with the outputs at
high impedance. Connecting SHDN to VDD and OE to GND
results in nap mode with the outputs at high impedance.
Connecting SHDN to VDD and OE to VDD results in sleep
mode with the outputs at high impedance.
If the clock duty cycle stabilizer is used, a >1s high pulse
shouldbeappliedtotheSHDNpinoncethepowersupplies
are stable at power up.
OE (Pin 11): Output Enable Pin. Refer to SHDN pin func-
tion.
NC (Pins 12, 13): Do not connect these pins.
D0 – D11 (Pins 14, 15, 16, 17, 18, 19, 22, 23, 24, 25,
26, 27): Digital Outputs. D11 is the MSB.
OGND (Pin 20): Output Driver Ground.
OVDD (Pin 21): Positive Supply for the Output Drivers.
Bypass to ground with 0.1F ceramic chip capacitor.
OF (Pin 28): Over/Under Flow Output. High when an over
or under flow has occurred.
MODE (Pin 29): Output Format and Clock Duty Cycle
Stabilizer Selection Pin. Connecting MODE to GND selects
offset binary output format and turns the clock duty cycle
stabilizer off. 1/3 VDD selects offset binary output format
and turns the clock duty cycle stabilizer on. 2/3 VDDselects
2’s complement output format and turns the clock duty
cycle stabilizer on. VDD selects 2’s complement output
format and turns the clock duty cycle stabilizer off.
SENSE(Pin30):ReferenceProgrammingPin.Connecting
SENSE to VCM selects the internal reference and a ±0.5V
input range. VDD selects the internal reference and a ±1V
input range. An external reference greater than 0.5V and
less than 1V applied to SENSE selects an input range of
±VSENSE. ±1V is the largest valid input range.
VCM (Pin 31): 1.5V Output and Input Common Mode Bias.
Bypass to ground with 2.2F ceramic chip capacitor.
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| LTC2226HLU#TRPBF | 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP32 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| LTC2226HLU#PBF | 功能描述:IC ADC 12BIT 25MSPS 32-TQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):12 采樣率（每秒）:3M 數(shù)據(jù)接口:- 轉(zhuǎn)換器數(shù)目:- 功率耗散（最大）:- 電壓電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 供應(yīng)商設(shè)備封裝:SOT-23-6 包裝:帶卷 (TR) 輸入數(shù)目和類型:- |
| LTC2226HLU#TRPBF | 制造商:Linear Technology 功能描述:ADC Single Pipelined 25Msps 12-bit Parallel 48-Pin LQFP T/R |
| LTC2226HLX | 制造商:LINER 制造商全稱:Linear Technology 功能描述:12-Bit, 25Msps 125°C ADC in LQFP |
| LTC2226HLX#PBF | 功能描述:IC ADC 12BIT 25MSPS 48-LQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):12 采樣率（每秒）:300k 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類型:1 個(gè)單端，單極；1 個(gè)單端，雙極 |
| LTC2226HLX-PBF | 制造商:LINER 制造商全稱:Linear Technology 功能描述:12-Bit, 25Msps 125°C ADC in LQFP |
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