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參數(shù)資料
| 型號(hào)： | LTC2225IUH#TRPBF |
| 廠(chǎng)商： | Linear Technology |
| 文件頁(yè)數(shù)： | 2/20頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT 10MSPS 3V 32-QFN |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 10M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 69mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 32-WFQFN 裸露焊盤(pán) |
| 供應(yīng)商設(shè)備封裝： | 32-QFN 裸露焊盤(pán)（5x5） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類(lèi)型： | 1 個(gè)單端，雙極; 1 個(gè)差分，雙極 |
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LTC2225
10
2225fa
Aperture Delay Time
The time from when CLK reaches mid-supply to the instant
that the input signal is held by the sample and hold circuit.
Aperture Delay Jitter
The variation in the aperture delay time from conversion to
conversion. This random variation will result in noise
when sampling an AC input. The signal to noise ratio due
to the jitter alone will be:
SNRJITTER = –20log (2π fIN tJITTER)
CONVERTER OPERATION
As shown in Figure 1, the LTC2225 is a CMOS pipelined
multistep converter. The converter has six pipelined ADC
stages; a sampled analog input will result in a digitized
value five cycles later (see the Timing Diagram section).
For optimal AC performance the analog inputs should be
driven differentially. For cost sensitive applications, the
analog inputs can be driven single-ended with slightly
worse harmonic distortion. The CLK input is single-ended.
The LTC2225 has two phases of operation, determined by
the state of the CLK input pin.
Each pipelined stage shown in Figure 1 contains an ADC,
a reconstruction DAC and an interstage residue amplifier.
In operation, the ADC quantizes the input to the stage and
the quantized value is subtracted from the input by the
DAC to produce a residue. The residue is amplified and
output by the residue amplifier. Successive stages operate
out of phase so that when the odd stages are outputting
their residue, the even stages are acquiring that residue
and vice versa.
When CLK is low, the analog input is sampled differentially
directly onto the input sample-and-hold capacitors, inside
the “Input S/H” shown in the block diagram. At the instant
that CLK transitions from low to high, the sampled input is
held. While CLK is high, the held input voltage is buffered
by the S/H amplifier which drives the first pipelined ADC
stage. The first stage acquires the output of the S/H during
this high phase of CLK. When CLK goes back low, the first
stage produces its residue which is acquired by the
second stage. At the same time, the input S/H goes back
to acquiring the analog input. When CLK goes back high,
the second stage produces its residue which is acquired
by the third stage. An identical process is repeated for the
third, fourth and fifth stages, resulting in a fifth stage
residue that is sent to the sixth stage ADC for final
evaluation.
Each ADC stage following the first has additional range to
accommodate flash and amplifier offset errors. Results
from all of the ADC stages are digitally synchronized such
that the results can be properly combined in the correction
logic before being sent to the output buffer.
SAMPLE/HOLD OPERATION AND INPUT DRIVE
Sample/Hold Operation
Figure 2 shows an equivalent circuit for the LTC2225
CMOS differential sample-and-hold. The analog inputs are
connected to the sampling capacitors (CSAMPLE) through
NMOS transistors. The capacitors shown attached to each
input (CPARASITIC) are the summation of all other capaci-
tance associated with each input.
Figure 2. Equivalent Input Circuit
During the sample phase when CLK is low, the transistors
connect the analog inputs to the sampling capacitors and
they charge to and track the differential input voltage.
When CLK transitions from low to high, the sampled input
voltage is held on the sampling capacitors. During the hold
phase when CLK is high, the sampling capacitors are
disconnected from the input and the held voltage is passed
to the ADC core for processing. As CLK transitions from
high to low, the inputs are reconnected to the sampling
APPLICATIO S I FOR ATIO
WU
UU
VDD
15
15
CPARASITIC
1pF
CPARASITIC
1pF
CSAMPLE
4pF
CSAMPLE
4pF
LTC2225
AIN+
AIN–
CLK
2225 F02
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LTC2226 | 制造商:LINER 制造商全稱(chēng):Linear Technology 功能描述:14-Bit, 125/105Msps Low Power 3V ADCs |
| LTC2226CUH | 制造商:Linear Technology 功能描述:ADC Single Pipelined 25Msps 12-bit Parallel 32-Pin QFN EP |
| LTC2226CUH#PBF | 功能描述:IC ADC 12BIT 25MSPS SAMPL 32-QFN RoHS:是 類(lèi)別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):16 采樣率（每秒）:45k 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:315mW 電壓電源:模擬和數(shù)字 工作溫度:0°C ~ 70°C 安裝類(lèi)型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:28-SOIC W 包裝:帶卷 (TR) 輸入數(shù)目和類(lèi)型:2 個(gè)單端，單極 |
| LTC2226CUH#TRPBF | 功能描述:IC ADC 12BIT 25MSPS SAMPL 32-QFN RoHS:是 類(lèi)別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):16 采樣率（每秒）:45k 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:315mW 電壓電源:模擬和數(shù)字 工作溫度:0°C ~ 70°C 安裝類(lèi)型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:28-SOIC W 包裝:帶卷 (TR) 輸入數(shù)目和類(lèi)型:2 個(gè)單端，單極 |
| LTC2226CUH-PBF | 制造商:LINER 制造商全稱(chēng):Linear Technology 功能描述:12-Bit, 65/40/25Msps Low Power 3V ADCs |
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