IOVDD vs Sample Rate, 5MHz Sine" />
參數(shù)資料
型號(hào)： LTC2225IUH#TRPBF
廠商： Linear Technology
文件頁(yè)數(shù)： 18/20頁(yè)
文件大?。?/td> 0K
描述： IC ADC 12BIT 10MSPS 3V 32-QFN
標(biāo)準(zhǔn)包裝： 2,500
位數(shù)： 12
采樣率（每秒）： 10M
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 69mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 32-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 32-QFN 裸露焊盤（5x5）
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 1 個(gè)單端，雙極; 1 個(gè)差分，雙極
LTC2225
7
2225fa
TYPICAL PERFOR A CE CHARACTERISTICS
UW
IOVDD vs Sample Rate, 5MHz Sine
Wave Input, –1dB, OVDD = 1.8V
IVDD vs Sample Rate,
5MHz Sine Wave Input, –1dB
UU
U
PI FU CTIO S
AIN+ (Pin 1): Positive Differential Analog Input.
AIN- (Pin 2): Negative Differential Analog Input.
REFH (Pins 3, 4): ADC High Reference. Short together and
bypass to pins 5, 6 with a 0.1
F ceramic chip capacitor as
close to the pin as possible. Also bypass to pins 5, 6 with
an additional 2.2
F ceramic chip capacitor and to ground
with a 1
F ceramic chip capacitor.
REFL (Pins 5, 6): ADC Low Reference. Short together and
bypass to pins 3, 4 with a 0.1
F ceramic chip capacitor as
close to the pin as possible. Also bypass to pins 3, 4 with
an additional 2.2
F ceramic chip capacitor and to ground
with a 1
F ceramic chip capacitor.
VDD (Pins 7, 32): 3V Supply. Bypass to GND with 0.1F
ceramic chip capacitors.
GND (Pin 8): ADC Power Ground.
CLK (Pin 9): Clock Input. The input sample starts on the
positive edge.
SHDN (Pin 10): Shutdown Mode Selection Pin. Connect-
ing SHDN to GND and OE to GND results in normal
operation with the outputs enabled. Connecting SHDN to
GND and OE to VDD results in normal operation with the
outputs at high impedance. Connecting SHDN to VDD and
OE to GND results in nap mode with the outputs at high
impedance. Connecting SHDN to VDD and OE to VDD
results in sleep mode with the outputs at high impedance.
OE (Pin 11): Output Enable Pin. Refer to SHDN pin
function.
NC (Pins 12, 13): Do Not Connect These Pins.
D0 – D11 (Pins 14, 15, 16, 17, 18, 19, 22, 23, 24, 25, 26,
27): Digital Outputs. D11 is the MSB.
OGND (Pin 20): Output Driver Ground.
OVDD (Pin 21): Positive Supply for the Output Drivers.
Bypass to ground with 0.1
F ceramic chip capacitor.
OF (Pin 28): Over/Under Flow Output. High when an over
or under flow has occurred.
MODE (Pin 29): Output Format and Clock Duty Cycle
Stabilizer Selection Pin. Connecting MODE to GND selects
offset binary output format and turns the clock duty cycle
stabilizer off. 1/3 VDD selects offset binary output format
and turns the clock duty cycle stabilizer on. 2/3 VDD selects
2’s complement output format and turns the clock duty
cycle stabilizer on. VDD selects 2’s complement output
format and turns the clock duty cycle stabilizer off.
SAMPLE RATE (Msps)
10
I VDD
(mA)
15
20
25
02468
2225 G12
10
12
14
2V RANGE
1V RANGE
SAMPLE RATE (Msps)
0
I OVDD
(mA)
0.1
0.3
0.4
0.5
1.0
0.7
4
8
10
2225 G13
0.2
0.8
0.9
0.6
2
6
12
14
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