參數(shù)資料
型號: LTC2206CUK-14#PBF
廠商: Linear Technology
文件頁數(shù): 6/32頁
文件大?。?/td> 0K
描述: IC ADC 14BIT 80MSPS 48-QFN
標(biāo)準(zhǔn)包裝: 52
位數(shù): 14
采樣率(每秒): 80M
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 875mW
電壓電源: 單電源
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 48-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 48-QFN-EP(7x7)
包裝: 管件
輸入數(shù)目和類型: 1 個差分
配用: DC890B-ND - BOARD USB DATA COLLECTION
LTC2207-14/LTC2206-14
14
220714614fc
TYPICAL PERFORMANCE CHARACTERISTICS
TIME AFTER WAKE-UP OR CLOCK START (μs)
0
FULL-SCALE
ERROR
(%)
0.2
0.6
1.0
400
2207614 G60
–0.2
–0.6
0
0.4
0.8
–0.4
–0.8
–1.0
100
50
200
150
300 350
450
250
500
TIME FROM WAKE-UP OR CLOCK START (μs)
0
FULL-SCALE
ERROR
(%)
1
3
5
800
2207614 G61
–1
–3
0
2
4
–2
–4
–5
200
100
400
300
600 700
900
500
1000
Mid-Scale Settling After Wake
Up from Shutdown or Starting
Encode Clock
Full-Scale Settling After Wake
Up from Shutdown or Starting
Encode Clock
SENSE (Pin 1): Reference Mode Select and External
Reference Input. Tie SENSE to VDD to select the internal
2.5V bandgap reference. An external reference of 2.5V or
1.25V may be used; both reference values will set a full
scale ADC range of 2.25V (PGA = 0).
VCM(Pin2):1.25VOutput.Optimumvoltageforinputcom-
mon mode. Must be bypassed to ground with a minimum
of 2.2μF. Ceramic chip capacitors are recommended.
VDD (Pins 3, 4, 12, 13, 14): 3.3V Analog Supply Pin.
Bypass to GND with 0.1μF ceramic chip capacitors.
GND (Pins 5, 8, 11, 15, 48): ADC Power Ground.
AIN+ (Pin 6): Positive Differential Analog Input.
AIN– (Pin 7): Negative Differential Analog Input.
ENC+ (Pin 9): Positive Differential Encode Input. The
sampled analog input is held on the rising edge of ENC+.
Internally biased to 1.6V through a 6.2k resistor. Output
data can be latched on the rising edge of ENC+.
ENC(Pin 10): Negative Differential Encode Input. The
sampled analog input is held on the falling edge of ENC.
Internally biased to 1.6V through a 6.2k resistor. Bypass to
ground with a 0.1μF capacitor for a single-ended Encode
signal.
SHDN (Pin 16): Power Shutdown Pin. SHDN = low results
in normal operation. SHDN = high results in powered
down analog circuitry and the digital outputs are placed
in a high impedance state.
DITH (Pin 17): Internal Dither Enable Pin. DITH = low
disables internal dither. DITH = high enables internal dither.
Refer to Internal Dither section of this data sheet for details
on dither operation.
NC (Pins 18, 19): No Connect.
D0-D13 (Pins 20-22, 26-28, 32-35 and 39-42): Digital
Outputs. D13 is the MSB.
OGND (Pins 23, 31 and 38): Output Driver Ground.
OVDD (Pins 24, 25, 36, 37): Positive Supply for the Output
Drivers. Bypass to ground with 0.1μF capacitor.
CLKOUT(Pin 29): Data Valid Output. CLKOUTwill toggle
at the sample rate. Latch the data on the falling edge of
CLKOUT.
CLKOUT+ (Pin 30): Inverted Data Valid Output. CLKOUT+
will toggle at the sample rate. Latch the data on the rising
edge of CLKOUT+.
PIN FUNCTIONS
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