參數(shù)資料
型號(hào): LTC2202C#TRPBF
廠商: LINEAR TECHNOLOGY CORP
元件分類: ADC
英文描述: 1-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC48
封裝: 7 X 7 MM, LEAD FREE, PLASTIC, MO-220-WKKD-2, QFN-48
文件頁數(shù): 8/26頁
文件大?。?/td> 1118K
代理商: LTC2202C#TRPBF
PREP
ARED
FOR
LTC2203/LTC2202
16
22032p
BLOCK DIAGRA
W
Figure 1. Functional Block Diagram
ADC CLOCKS
DIFFERENTIAL
INPUT
LOW JITTER
CLOCK
DRIVER
DITHER
SIGNAL
GENERATOR
FIRST PIPELINED
ADC STAGE
FIFTH PIPELINED
ADC STAGE
FOURTH PIPELINED
ADC STAGE
SECOND PIPELINED
ADC STAGE
CLK
CORRECTION LOGIC
AND
SHIFT REGISTER
DITH
M0DE
OGND
CLKOUT+
CLKOUT–
OF
D15
D14
OVDD
D1
D0
22032 F01
INPUT
S/H
AIN–
AIN+
THIRD PIPELINED
ADC STAGE
OUTPUT
DRIVERS
CONTROL
LOGIC
PGA
RAND
SHDN
VDD
GND
PGA
SENSE
VCM
BUFFER
ADC
REFERENCE
VOLTAGE
REFERENCE
RANGE
SELECT
MODE (Pin 45): Output Format and Clock Duty Cycle
Stabilizer Selection Pin. Connecting MODE to 0V selects
offset binary output format and disables the clock duty
cycle stabilizer. Connecting MODE to 1/3VDDselectsoffset
binary output format and enables the clock duty cycle sta-
bilizer.ConnectingMODEto2/3VDDselects2’scomplement
output format and enables the clock duty cycle stabilizer.
Connecting MODE to VDD selects 2’s complement output
format and disables the clock duty cycle stabilizer.
RAND(Pin46):DigitalOutputRandomizationSelectionPin.
RAND low results in normal operation. RAND high selects
D1-D15 to be EXCLUSIVE-ORed with D0 (the LSB). The
outputcanbedecodedbyagainapplyinganXORoperation
between the LSB and all other bits. The mode of operation
reduces the effects of digital output interference.
PGA(Pin47):ProgrammableGainAmplierControlPin.Low
selects a front-end gain of 1, input range of 2.5VP-P. High
selects a front-end gain of 1.5, input range of 1.667VP-P.
GND (Exposed Pad, Pin 49): ADC Power Ground. The ex-
posed pad on the bottom of the package must be soldered
to ground.
U
PI FU CTIO S
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