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參數(shù)資料
| 型號： | LTC2202C#TRPBF |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | ADC |
| 英文描述： | 1-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC48 |
| 封裝： | 7 X 7 MM, LEAD FREE, PLASTIC, MO-220-WKKD-2, QFN-48 |
| 文件頁數(shù)： | 10/26頁 |
| 文件大小： | 1118K |
| 代理商： | LTC2202C#TRPBF |
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PREP
ARED
FOR
LTC2203/LTC2202
18
22032p
CONVERTER OPERATION
TheLTC2203/LTC2202areCMOSpipelinedmultistepcon-
verterswithafront-endPGA.AsshowninFigure1,thecon-
verterhasvepipelinedADCstages;asampledanaloginput
will result in a digitized value seven cycles later (see the
TimingDiagramsection).Theanaloginputisdifferentialfor
improvedcommonmodenoiseimmunityandtomaximize
the input range. Additionally, the differential input drive
will reduce even order harmonics of the sample-and-hold
circuit.
Each pipelined stage shown in Figure 1 contains an ADC,
a reconstruction DAC and an interstage amplier. In
operation, the ADC quantizes the input to the stage and
the quantized value is subtracted from the input by the
DAC to produce a residue. The residue is amplied and
output by the residue amplier. Successive stages oper-
ate out of phase so that when odd stages are outputting
their residue, the even stages are acquiring that residue
and vice versa.
The phase of operation is determined by the state of the
CLK input pin.
When CLK is high, the analog input is sampled differen-
tially directly onto the input sample-and-hold capacitors,
inside the “input S/H” shown in the block diagram. At the
instant that CLK transitions from high to low, the voltage
on the sample capacitors is held. While CLK is low, the
held input voltage is buffered by the S/H amplier which
drivestherstpipelinedADCstage.Therststageacquires
the output of the S/H amplier during the low phase of
CLK. When CLK goes back high, the rst stage produces
its residue which is acquired by the second stage. At the
sametime,theinputS/Hgoesbacktoacquiringtheanalog
input. When CLK goes low, the second stage produces its
residue which is acquired by the third stage. An identi-
cal process is repeated for the third and fourth stages,
resulting in a fourth stage residue that is sent to the fth
stage for nal evaluation.
Each ADC stage following the rst has additional range to
accommodate ash and amplier offset errors. Results
from all of the ADC stages are digitally delayed such that
the results can be properly combined in the correction
logic before being sent to the output buffer.
APPLICATIO S I FOR ATIO
W
U
SAMPLE/HOLD OPERATION AND INPUT DRIVE
Sample/Hold Operation
Figure 2 shows an equivalent circuit for the LTC2203/
LTC2202 CMOS differential sample and hold. The differ-
ential analog inputs are sampled directly onto sampling
capacitors (CSAMPLE) through NMOS transitors. The
capacitors shown attached to each input (CPARASITIC) are
the summation of all other capacitance associated with
each input.
During the sample phase when CLK is high, the NMOS
transistors connect the analog inputs to the sampling
capacitors and they charge to, and track the differential
input voltage. When CLK transitions from high to low, the
sampled input voltage is held on the sampling capacitors.
During the hold phase when CLK is high, the sampling
capacitors are disconnected from the input and the held
voltage is passed to the ADC core for processing. As CLK
transitions from low to high, the inputs are reconnected to
the sampling capacitors to acquire a new sample. Since
the sampling capacitors still hold the previous sample,
a charging glitch proportional to the change in voltage
between samples will be seen at this time at the input of
the converter. If the change between the last sample and
Figure 2. Equivalent Input Circuit
CSAMPLE
9.1pF
VDD
V
LTC220
CLK
3/02
AIN+
22032 F02
CSAMPLE
9.1pF
VDD
AIN–
CPARASITIC
1.8pF
CPARASITIC
1.8pF
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LTC2202CUK | 制造商:Linear Technology 功能描述:Single ADC Pipelined 10Msps 16-bit Parallel 48-Pin QFN EP |
| LTC2202CUK#PBF | 功能描述:IC ADC 16-BIT 10MSPS 48-QFN RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:microPOWER™ 位數(shù):8 采樣率（每秒）:1M 數(shù)據(jù)接口:串行，SPI? 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:- 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:24-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-VQFN 裸露焊盤（4x4） 包裝:Digi-Reel® 輸入數(shù)目和類型:8 個單端，單極 產(chǎn)品目錄頁面:892 (CN2011-ZH PDF) 其它名稱:296-25851-6 |
| LTC2202CUK#TRPBF | 功能描述:IC ADC 16-BIT 10MSPS 48-QFN RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個單端，雙極 |
| LTC2202CUKPBF | 制造商:Linear Technology 功能描述:ADC 16-Bit 10Msps 81.6dB SNR QFN48 |
| LTC2202IUK | 制造商:Linear Technology 功能描述:ADC Single Pipelined 10Msps 16-bit Parallel 48-Pin QFN EP |
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