參數(shù)資料
型號(hào)： LTC2182CUP#PBF
廠(chǎng)商： LINEAR TECHNOLOGY CORP
元件分類(lèi)： ADC
英文描述： 2-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64
封裝： 9 X 9 MM, LEAD FREE, PLASTIC, MO-220WNJR-5, QFN-64
文件頁(yè)數(shù)： 35/36頁(yè)
文件大小： 3836K
代理商： LTC2182CUP#PBF
LTC2182/LTC2181/LTC2180
8
218210f
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Digital Data Outputs (LVDS Mode)
tD
ENC to Data Delay
CL = 5pF (Note 8)
l
1.1
1.8
3.2
ns
tC
ENC to CLKOUT Delay
CL = 5pF (Note 8)
l
1
1.5
2.7
ns
tSKEW
DATA to CLKOUT Skew
tD – tC (Note 8)
l
0
0.3
0.6
ns
Pipeline Latency
6.5
Cycles
SPI Port Timing (Note 8)
tSCK
SCK Period
Write Mode
Readback Mode, CSDO = 20pF, RPULLUP = 2k
l
40
250
ns
tS
CS to SCK Setup Time
l
5
ns
tH
SCK to CS Setup Time
l
5
ns
tDS
SDI Setup Time
l
5
ns
tDH
SDI Hold Time
l
5
ns
tDO
SCK Falling to SDO Valid
Readback Mode, CSDO = 20pF, RPULLUP = 2k
l
125
ns
TIMING CHARACTERISTICS The
l
denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND with GND and OGND
shorted (unless otherwise noted).
Note 3: When these pin voltages are taken below GND or above VDD, they
will be clamped by internal diodes. This product can handle input currents
of greater than 100mA below GND or above VDD without latchup.
Note 4: When these pin voltages are taken below GND they will be
clamped by internal diodes. When these pin voltages are taken above VDD
they will not be clamped by internal diodes. This product can handle input
currents of greater than 100mA below GND without latchup.
Note 5: VDD = OVDD = 1.8V, fSAMPLE = 65MHz (LTC2182), 40MHz
(LTC2181), or 25MHz (LTC2180), LVDS outputs, differential ENC+/ENC– =
2VP-P sine wave, input range = 2VP-P with differential drive, unless
otherwise noted.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
best fit straight line to the transfer curve. The deviation is measured from
the center of the quantization band.
Note 7: Offset error is the offset voltage measured from –0.5 LSB when
the output code flickers between 0000 0000 0000 0000 and 1111 1111
1111 1111 in 2’s complement output mode.
Note 8: Guaranteed by design, not subject to test.
Note 9: VDD = 1.8V, fSAMPLE = 65MHz (LTC2182), 40MHz (LTC2181), or
25MHz (LTC2180), CMOS outputs, ENC+ = single-ended 1.8V square
wave, ENC– = 0V, input range = 2VP-P with differential drive, 5pF load on
each digital output unless otherwise noted. The supply current and power
dissipation specifications are totals for the entire IC, not per channel.
Note 10: Recommended operating conditions.
相關(guān)PDF資料
PDF描述
LTC2182IUP#PBF 2-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64
LTC2181IUP#PBF 2-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64
LTC2181IUP#TRPBF 2-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64
LTC2180IUP#PBF 2-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64
LTC2180IUP#TRPBF 2-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LTC2182IUP#PBF 制造商:Linear Technology 功能描述:ADC Dual 65Msps 16-bit Parallel/Serial (SPI)/LVDS 64-Pin QFN EP 制造商:Linear Technology 功能描述:IC ADC 16BIT DUAL PAR/SRL 64QFN
LTC2182IUP#PBF-ES 制造商:Linear Technology 功能描述:ADC Dual 65Msps 16-bit Parallel/Serial (SPI)/LVDS 64-Pin QFN EP
LTC2182IUP#TRPBF 制造商:Linear Technology 功能描述:ADC Dual 65Msps 16-bit Parallel/Serial (SPI)/LVDS 64-Pin QFN EP T/R 制造商:Linear Technology 功能描述:IC ADC DUAL 16BIT 65MSPS 64-QFN
LTC2182IUP#TRPBF-ES 制造商:Linear Technology 功能描述:ADC Dual 65Msps 16-bit Parallel/Serial (SPI)/LVDS 64-Pin QFN EP T/R
LTC2183 制造商:LINER 制造商全稱(chēng):Linear Technology 功能描述:16-Bit, 125/105/80Msps Low Power Dual ADCs
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