參數(shù)資料
型號(hào)： LTC2182CUP#PBF
廠商： LINEAR TECHNOLOGY CORP
元件分類(lèi)： ADC
英文描述： 2-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64
封裝： 9 X 9 MM, LEAD FREE, PLASTIC, MO-220WNJR-5, QFN-64
文件頁(yè)數(shù)： 11/36頁(yè)
文件大?。?/td> 3836K
代理商： LTC2182CUP#PBF
19
218210f
LTC2182/LTC2181/LTC2180
CONVERTER OPERATION
The LTC2182/LTC2181/LTC2180 are low power, two-
channel, 16-bit, 65Msps/40Msps/25Msps A/D convert-
ers that are powered by a single 1.8V supply. The analog
inputs should be driven differentially. The encode input
can be driven differentially, or single ended for lower
power consumption. The digital outputs can be CMOS,
double data rate CMOS (to halve the number of output
lines), or double data rate LVDS (to reduce digital noise
in the system.) Many additional features can be chosen
by programming the mode control registers through a
serial SPI port.
ANALOG INPUT
The analog inputs are differential CMOS sample-and-hold
circuits (Figure 2). The inputs should be driven differen-
tially around a common mode voltage set by the VCM1 or
VCM2 output pins, which are nominally VDD/2. For the 2V
input range, the inputs should swing from VCM – 0.5V
to VCM + 0.5V. There should be 180° phase difference
between the inputs.
The two channels are simultaneously sampled by a shared
encode circuit (Figure 2).
Single-Ended Input
For applications less sensitive to harmonic distortion, the
AIN+ input can be driven single-ended with a 1VP-P signal
centered around VCM. The AIN– input should be connected
to VCM and the VCM bypass capacitor should be increased
to 2.2F. With a single-ended input the harmonic distortion
and INL will degrade, but the noise and DNL will remain
unchanged.
INPUT DRIVE CIRCUITS
Input filtering
If possible, there should be an RC lowpass filter right at
the analog inputs. This lowpass filter isolates the drive
circuitry from the A/D sample-and-hold switching, and
alsolimitswidebandnoisefromthedrivecircuitry.Figure 3
shows an example of an input RC filter. The RC component
values should be chosen based on the application’s input
frequency.
Transformer Coupled Circuits
Figure 3 shows the analog input being driven by an RF
transformer with a center-tapped secondary. The center
tap is biased with VCM, setting the A/D input at its optimal
DC level. At higher input frequencies a transmission line
baluntransformer(Figure4toFigure6)hasbetterbalance,
resulting in lower A/D distortion.
CSAMPLE
5pF
RON
15
RON
15
VDD
LTC2182
AIN+
218210 F02
CSAMPLE
5pF
VDD
AIN–
ENC–
ENC+
1.2V
10k
1.2V
10k
CPARASITIC
1.8pF
CPARASITIC
1.8pF
10
25
50
0.1F
AIN+
AIN–
12pF
0.1F
VCM
LTC2182
ANALOG
INPUT
0.1F
T1
1:1
T1: MA/COM MABAES0060
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
218210 F03
Figure 2. Equivalent Input Circuit. Only One of the Two
Analog Channels Is Shown
Figure 3. Analog Input Circuit Using a Transformer.
Recommended for Input Frequencies from 5MHz to 70MHz
APPLICATIONS INFORMATION
相關(guān)PDF資料
PDF描述
LTC2182IUP#PBF 2-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64
LTC2181IUP#PBF 2-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64
LTC2181IUP#TRPBF 2-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64
LTC2180IUP#PBF 2-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64
LTC2180IUP#TRPBF 2-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LTC2182IUP#PBF 制造商:Linear Technology 功能描述:ADC Dual 65Msps 16-bit Parallel/Serial (SPI)/LVDS 64-Pin QFN EP 制造商:Linear Technology 功能描述:IC ADC 16BIT DUAL PAR/SRL 64QFN
LTC2182IUP#PBF-ES 制造商:Linear Technology 功能描述:ADC Dual 65Msps 16-bit Parallel/Serial (SPI)/LVDS 64-Pin QFN EP
LTC2182IUP#TRPBF 制造商:Linear Technology 功能描述:ADC Dual 65Msps 16-bit Parallel/Serial (SPI)/LVDS 64-Pin QFN EP T/R 制造商:Linear Technology 功能描述:IC ADC DUAL 16BIT 65MSPS 64-QFN
LTC2182IUP#TRPBF-ES 制造商:Linear Technology 功能描述:ADC Dual 65Msps 16-bit Parallel/Serial (SPI)/LVDS 64-Pin QFN EP T/R
LTC2183 制造商:LINER 制造商全稱(chēng):Linear Technology 功能描述:16-Bit, 125/105/80Msps Low Power Dual ADCs
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