AIN1+ (Pin 1): Channel 1 Positive Diffe" />
參數(shù)資料
型號(hào)： LTC2170IUKG-14#TRPBF
廠商： Linear Technology
文件頁(yè)數(shù)： 9/34頁(yè)
文件大?。?/td> 0K
描述： IC ADC 14BIT SER/PAR 25M 52-QFN
標(biāo)準(zhǔn)包裝： 2,000
位數(shù)： 14
采樣率（每秒）： 25M
數(shù)據(jù)接口： Serial LVDS
轉(zhuǎn)換器數(shù)目： 4
功率耗散（最大）： 243mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 52-WFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 52-QFN（7x8）
包裝： 帶卷 (TR)
輸入數(shù)目和類(lèi)型： 2 Differential; 2 Single-Ended
配用： DC1525A-L-ND - BOARD DEMO 40MSPS LTC2170-12
DC1371A-ND - BOARD USB DATA ACQUISITION HS
LTC2172-14/
LTC2171-14/LTC2170-14
17
21721014fb
AIN1+ (Pin 1): Channel 1 Positive Differential Analog
Input.
AIN1– (Pin 2): Channel 1 Negative Differential Analog
Input.
VCM12 (Pin 3): Common Mode Bias Output, Nominally
Equal to VDD/2. VCM should be used to bias the common
mode of the analog inputs of channels 1 and 2. Bypass
to ground with a 0.1F ceramic capacitor.
AIN2+ (Pin 4): Channel 2 Positive Differential Analog
Input.
AIN2– (Pin 5): Channel 2 Negative Differential Analog
Input.
REFH (Pins 6, 7): ADC High Reference. Bypass to Pin 8
and Pin 9 with a 2.2F ceramic capacitor, and to ground
with a 0.1F ceramic capacitor.
REFL (Pins 8, 9): ADC Low Reference. Bypass to Pin 6
and Pin 7 with a 2.2F ceramic capacitor, and to ground
with a 0.1F ceramic capacitor.
AIN3+ (Pin 10): Channel 3 Positive Differential Analog
Input.
AIN3– (Pin 11): Channel 3 Negative Differential Analog
Input.
VCM34 (Pin 12): Common Mode Bias Output, Nominally
Equal to VDD/2. VCM should be used to bias the common
mode of the analog inputs of channels 3 and 4. Bypass
to ground with a 0.1F ceramic capacitor.
AIN4+ (Pin 13): Channel 4 Positive Differential Analog
Input.
AIN4– (Pin 14): Channel 4 Negative Differential Analog
Input.
VDD (Pins 15, 16, 51, 52): 1.8V Analog Power Supply.
Bypass to ground with 0.1F ceramic capacitors. Adjacent
pins can share a bypass capacitor.
ENC+ (Pin 17): Encode Input. Conversion starts on the
rising edge.
ENC– (Pin 18): Encode Complement Input. Conversion
starts on the falling edge.
CS(Pin19):Inserialprogrammingmode(PAR/SER=0V),
CS is the serial interface chip select input. When CS is low,
SCK is enabled for shifting data on SDI into the mode
controlregisters.Inparallelprogrammingmode(PAR/SER
= VDD), CS selects two-lane or one-lane output mode. CS
can be driven with 1.8V to 3.3V logic.
SCK (Pin 20): In serial programming mode (PAR/SER
= 0V), SCK is the serial interface clock input. In parallel
programming mode (PAR/SER = VDD),SCKselects3.5mA
or 1.75mA LVDS output currents. SCK can be driven with
1.8V to 3.3V logic.
SDI (Pin 21): In serial programming mode (PAR/SER =
0V), SDI is the serial interface data input. Data on SDI
is clocked into the mode control registers on the rising
edge of SCK. In parallel programming mode (PAR/SER =
VDD), SDI can be used to power down the part. SDI can
be driven with 1.8V to 3.3V logic.
GND (Pins 22, 45, 49, Exposed Pad Pin 53): ADC Power
Ground. The exposed pad must be soldered to the PCB
ground.
OGND (Pin 33): Output Driver Ground. Must be shorted
to the ground plane by a very low inductance path. Use
multiple vias close to the pin.
OVDD (Pin 34): Output Driver Supply. Bypass to ground
with a 0.1F ceramic capacitor.
SDO (Pin 46): In serial programming mode (PAR/SER
= 0V), SDO is the optional serial interface data output.
Data on SDO is read back from the mode control registers
and can be latched on the falling edge of SCK. SDO is
an open-drain N-channel MOSFET output that requires
an external 2k pull-up resistor of 1.8V to 3.3V. If read-
back from the mode control registers is not needed,
the pull-up resistor is not necessary and SDO can be
left unconnected. In parallel programming mode (PAR/
SER = VDD), SDO is an input that enables internal 100
termination resistors on the digital outputs. When used
as an input, SDO can be driven with 1.8V to 3.3V logic
through a 1k series resistor.
pin FuncTions
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