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參數(shù)資料
| 型號： | LTC2161CUK#TRPBF |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | ADC |
| 英文描述： | 1-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC48 |
| 封裝： | 7 X 7 MM, LEAD FREE, PLASTIC, MO-220WKKD-2, QFN-48 |
| 文件頁數(shù)： | 8/36頁 |
| 文件大?。?/td> | 651K |
| 代理商： | LTC2161CUK#TRPBF |
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LTC2162/LTC2161/LTC2160
16
216210f
pin FuncTions
(Pins that are the Same for All Digital Output Modes)
VCM (Pin 1): Common Mode Bias Output. Nominally
equal to VDD/2. VCM should be used to bias the common
mode of the analog inputs. Bypass to ground with a 0.1F
ceramic capacitor.
AIN+ (Pin 2): Positive Differential Analog Input.
AIN– (Pin 3): Negative Differential Analog Input.
GND (Pins 4, 10, 11, 14, 20, 43, Exposed Pad Pin 49):
ADC Power Ground. The exposed pad must be soldered
to the PCB ground.
REFH (Pins 5, 7): ADC High Reference. See the Applica-
tions Information section for recommended bypassing
circuits for REFH and REFL.
REFL(Pins6,8):ADCLowReference.SeetheApplications
Information section for recommended bypassing circuits
for REFH and REFL.
PAR/SER (Pin 9): Programming Mode Selection Pin. Con-
nect to ground to enable the serial programming mode.
CS, SCK, SDI, SDO become a serial interface that control
the A/D operating modes. Connect to VDD to enable the
parallel programming mode where CS, SCK, SDI, SDO
become parallel logic inputs that control a reduced set of
the A/D operating modes. PAR/SER should be connected
directlytogroundorVDDandnotbedrivenbyalogicsignal.
VDD (Pins 12, 13, 47, 48): Analog Power Supply, 1.7V
to 1.9V. Bypass to ground with 0.1F ceramic capacitors.
Adjacent pins can share a bypass capacitor.
ENC+ (Pin 15): Encode Input. Conversion starts on the
rising edge.
ENC– (Pin 16): Encode Complement Input. Conversion
starts on the falling edge. Tie to GND for single-ended
encode mode.
CS (Pin 17): Serial Interface Chip Select Input. In serial
programming mode (PAR/SER = 0V), CS is the serial in-
terface chip select input. When CS is low, SCK is enabled
for shifting data on SDI into the mode control registers.
In the parallel programming mode (PAR/SER = VDD),
CS controls the clock duty cycle stabilizer (see Table 2).
CS can be driven with 1.8V to 3.3V logic.
SCK (Pin 18): Serial Interface Clock Input. In serial
programming mode, (PAR/SER = 0V), SCK is the serial
interface clock input. In the parallel programming mode
(PAR/SER = VDD), SCK controls the digital output mode
(see Table 2). SCK can be driven with 1.8V to 3.3V logic.
SDI(Pin19):SerialInterfaceDataInput.Inserialprogram-
ming mode, (PAR/SER = 0V), SDI is the serial interface
data input. Data on SDI is clocked into the mode control
registersontherisingedgeofSCK.Intheparallelprogram-
ming mode (PAR/SER = VDD), SDI can be used together
with SDO to power down the part (Table 2). SDI can be
driven with 1.8V to 3.3V logic.
OGND (Pin 31): Output Driver Ground. Must be shorted
to the ground plane by a very low inductance path. Use
multiple vias close to the pin.
OVDD (Pin 32): Output Driver Supply. Bypass to ground
with a 0.1F ceramic capacitor.
SDO (Pin 44): Serial Interface Data Output. In serial pro-
gramming mode, (PAR/SER = 0V), SDO is the optional
serial interface data output. Data on SDO is read back from
the mode control registers and can be latched on the fall-
ing edge of SCK. SDO is an open-drain NMOS output that
requires an external 2k pull-up resistor to 1.8V – 3.3V. If
read back from the mode control registers is not needed,
the pull-up resistor is not necessary and SDO can be left
unconnected.Intheparallelprogrammingmode(PAR/SER
= VDD), SDO can be used together with SDI to power down
the part (Table 2). When used as an input, SDO can be
driven with 1.8V to 3.3V logic through a 1k series resistor.
VREF (Pin 45): Reference Voltage Output. Bypass to
ground with a 2.2F ceramic capacitor. The output voltage
is nominally 1.25V.
SENSE(Pin46): ReferenceProgrammingPin.Connecting
SENSEtoVDDselectstheinternalreferenceanda±1Vinput
range. Connecting SENSE to ground selects the internal
reference and a ±0.5V input range. An external reference
between 0.625V and 1.3V applied to SENSE selects an
input range of ±0.8 VSENSE.
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| LTC2161IUK#PBF | 制造商:Linear Technology 功能描述:ADC Single 40Msps 16-bit Parallel/Serial (SPI)/LVDS 48-Pin QFN EP 制造商:Linear Technology 功能描述:IC ADC 16BIT 40 MSPS 48-QFN |
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| LTC2162CUK#PBF | 制造商:Linear Technology 功能描述:ADC Single 65Msps 16-bit Parallel/Serial (SPI)/LVDS 48-Pin QFN EP 制造商:Linear Technology 功能描述:IC ADC 16BIT 65 MSPS 48-QFN 制造商:Linear Technology 功能描述:ADC 16BIT 65MSPS 48QFN 制造商:Linear Technology 功能描述:ADC, 16BIT, 65MSPS, 48QFN |
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