參數(shù)資料
型號(hào)： LTC2155IUP-14#PBF
廠商： LINEAR TECHNOLOGY CORP
元件分類(lèi)： ADC
英文描述： 2-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64
封裝： 9 X 9 MM, LEAD FREE, PLASTIC, MO-220WNJR-5, QFN-64
文件頁(yè)數(shù)： 6/32頁(yè)
文件大?。?/td> 647K
代理商： LTC2155IUP-14#PBF
LTC2157-14/
LTC2156-14/LTC2155-14
14
21576514f
PIN FUNCTIONS
LVDS Outputs
The following pins are differential LVDS outputs. The
output current level is programmable. There is an optional
internal 100Ω termination resistor between the pins of
each LVDS output pair.
OF–/OF+ (Pins 22/23):
Over/Underflow Digital Output.
OF+ is high when an overflow or underflow has occurred.
The overflows for channel A and channel B are multiplexed
together.
DB0_1–/DB0_1+ to DB12_13–/DB12_13+ (Pins 24/25, 26/27,
28/29, 30/31, 34/35, 36/37, 38/39): Channel B Double
Data Rate Digital Outputs. Two data bits are multiplexed
onto each differential output pair. The even data bits (DB0,
DB2, DB4, DB6, DB8, DB10, DB12) appear when CLKOUT+
is low. The odd data bits (DB1, DB3, DB5, DB7, DB9, DB11,
DB13) appear when CLKOUT+ is high.
CLKOUT–/CLKOUT+ (Pins 40/41):
Data Output Clock.
The digital outputs normally transition at the same time
as the falling and rising edges of CLKOUT+. The phase of
CLKOUT+ can also be delayed relative to the digital outputs
by programming the mode control registers.
DA0_1–/DA0_1+ to DA12_13–/DA12_13+ (Pins 42/43, 44/45,
46/47, 50/51, 52/53, 54/55, 56/57): Channel A Double
Data Rate Digital Outputs. Two data bits are multiplexed
onto each differential output pair. The even data bits (DA0,
DA2, DA4, DA6, DA8, DA10, DA12) appear when CLKOUT+
is low. The odd data bits (DA1, DA3, DA5, DA7, DA9, DA11,
DA13) appear when CLKOUT+ is high.
FUNCTIONAL BLOCK DIAGRAM
Figure 1. Functional Block Diagram
S/H
VCM
BUFFER
GND
VCM
0.1μF
CORRECTION
LOGIC
OUTPUT
DRIVERS
14-BIT
PIPELINED
ADC CORE
CLOCK/DUTY
CYCLE CONTROL
1.25V
REFERENCE
RANGE
SELECT
CLOCK
ANALOG
INPUT
21576514 F01
DDR
LVDS
DDR
LVDS
VDD
OVDD
OGND
CS
CHANNEL A
CHANNEL B
S/H
CORRECTION
LOGIC
OUTPUT
DRIVERS
SPI
14-BIT
PIPELINED
ADC CORE
ANALOG
INPUT
OVDD
OGND
VREF
2.2μF
GND
SENSE
SCK
SDI
PAR/SER
DA12_13
DA0_1
DB12_13
DB0_1
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參數(shù)描述
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