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參數(shù)資料
| 型號： | LTC2155IUP-14#PBF |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | ADC |
| 英文描述： | 2-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64 |
| 封裝： | 9 X 9 MM, LEAD FREE, PLASTIC, MO-220WNJR-5, QFN-64 |
| 文件頁數(shù)： | 17/32頁 |
| 文件大?。?/td> | 647K |
| 代理商： | LTC2155IUP-14#PBF |
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LTC2157-14/
LTC2156-14/LTC2155-14
24
21576514f
APPLICATIONS INFORMATION
Table 3. Serial Programming Mode Register Map (PAR/SER = GND). X Indicates Unused Bit
REGISTER A0: RESET REGISTER (ADDRESS 00h) Write Only
D7
D6
D5
D4
D3
D2
D1
D0
RESET
XXXXXX
X
Bit 7
RESET
Software Reset Bit
0 = Reset Disabled
1 = Software Reset. All mode control registers are reset to 00h. This bit is automatically set back to zero after the reset is complete.
Bits 6-0
Unused Bits
REGISTER A1: POWER-DOWN REGISTER (ADDRESS 01h)
D7
D6
D5
D4
D3
D2
D1
D0
XXXX
SLEEP
NAP
PDB
0
Bits 7-4
Unused, this bit read back as 0
Bit 3
SLEEP
0 = Normal Operation
1 = Power Down Entire ADC
Bit 2
NAP
0 = Normal Mode
1 = Low Power Mode for Both Channels
Bit 1
PDB
0 = Normal Operation
1 = Power Down Channel B. Channel A operates normally.
Bit 0
Must be set to 0
REGISTER A2: TIMING REGISTER (ADDRESS 02h)
D7
D6
D5
D4
D3
D2
D1
D0
XXXX
CLKINV
CLKPHASE1
CLKPHASE0
DCS
Bits 7-4
Unused, This Bit Read Back as 0
Bit 3
CLKINV
Output Clock Invert Bit
0 = Normal CLKOUT Polarity (as shown in the Timing Diagrams)
1 = Inverted CLKOUT Polarity
Bits 2-1
CLKPHASE1:CLKPHASE0
Output Clock Phase Delay Bits
00 = No CLKOUT Delay (as shown in the Timing Diagrams)
01 = CLKOUT+/CLKOUT– delayed by 45° (Clock Period 1/8)
10 = CLKOUT+/CLKOUT– delayed by 90° (Clock Period 1/4)
11 = CLKOUT+/CLKOUT– delayed by 135° (Clock Period 3/8)
Note: If the CLKOUT phase delay feature is used, the clock duty cycle stabilizer must also be turned on.
Bit 0
DCS
Clock Duty Cycle Stabilizer Bit
0 = Clock Duty Cycle Stabilizer Off
1 = Clock Duty Cycle Stabilizer On
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