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參數(shù)資料
| 型號： | LTC2152IUP-14#PBF |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | ADC |
| 英文描述： | 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC40 |
| 封裝： | 6 X 6 MM, LEAD FREE, PLASTIC, QFN-40 |
| 文件頁數(shù)： | 8/32頁 |
| 文件大?。?/td> | 4005K |
| 代理商： | LTC2152IUP-14#PBF |
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LTC2152-14/
LTC2151-14/LTC2150-14
16
21521014p
PIN FUNCTIONS
LVDS Outputs (DDR LVDS)
The following pins are differential LVDS outputs. The
output current level is programmable. There is an optional
internal 100 termination resistor between the pins of
each LVDS output pair.
D0_1–/D0_1+ to D12_13–/D12_13+ (Pins 16/17, 18/19,
22/23, 24/25, 28/29, 31/32, 33/34): Double-Data Rate
Digital Outputs. Two data bits are multiplexed onto each
differential output pair. The even data bits (D0, D2, D4,
D6, D8, D10, D12) appear when CLKOUT+ is low. The odd
data bits (D1, D3, D5, D7, D9, D11, D13) appear when
CLKOUT+ is high.
CLKOUT–/CLKOUT+ (Pins 26/27): Data Output Clock.
The digital outputs normally transition at the same time
as the falling and rising edges of CLKOUT+. The phase of
CLKOUT+ can also be delayed relative to the digital outputs
by programming the mode control registers.
OF–/OF+ (Pins 14/15): Over/Underflow Digital Output.
OF+ is high when an overflow or underflow has occurred.
This underflow is valid only when CLKOUT+ is low. In the
second half clock cycle, the overflow is set to 0.
FUNCTIONAL BLOCK DIAGRAM
Figure 1. Functional Block Diagram
S/H
VCM
BUFFER
GND
VCM
0.1F
CORRECTION
LOGIC
OUTPUT
DRIVERS
14-BIT
PIPELINED
ADC
CLOCK/DUTY
CYCLE CONTROL
1.25V
REFERENCE
RANGE
SELECT
CLOCK
ANALOG
INPUT
21521014 F01
LVDS
VDD
OVDD
OGND
CS
SPI
VREF
2.2F
GND
SENSE
SCK
SDI
SDO
PAR/SER
D12_13
D0_1
相關(guān)PDF資料 |
PDF描述 |
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| LTC2150CUP-14#TRPBF | 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC40 |
| LTC2152CUP-14#TRPBF | 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC40 |
| LTC2150CUP-14#PBF | 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC40 |
| LTC2151CUP-14#TRPBF | 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC40 |
| LTC2157CUP-14#PBF | 2-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LTC2153-14 | 制造商:LINER 制造商全稱:Linear Technology 功能描述:300MHz to 4GHz Active Downconverting Mixer |
| LTC2153CUJ-14#PBF | 功能描述:IC ADC 14BIT DUAL 310MSPS 40QFN RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:250 系列:- 位數(shù):12 采樣率（每秒）:1.8M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:1.82W 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-LQFP 供應(yīng)商設(shè)備封裝:48-LQFP（7x7） 包裝:管件 輸入數(shù)目和類型:2 個單端，單極 |
| LTC2153CUJ-14#TRPBF | 功能描述:IC ADC 14BIT DUAL 310MSPS 40QFN RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:250 系列:- 位數(shù):12 采樣率（每秒）:1.8M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:1.82W 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-LQFP 供應(yīng)商設(shè)備封裝:48-LQFP（7x7） 包裝:管件 輸入數(shù)目和類型:2 個單端，單極 |
| LTC2153IUJ-12#PBF | 制造商:Linear Technology 功能描述:IC ADC 12BIT DUAL 310MSPS 制造商:Linear Technology 功能描述:MS-ADC/High Speed, 12-bit, 310Msps, 1.8V ADC, DDR LVDS Outputs |
| LTC2153IUJ-12#TRPBF | 制造商:Linear Technology 功能描述:IC ADC 12BIT DUAL 310MSPS 制造商:Linear Technology 功能描述:MS-ADC/High Speed, 12-bit, 310Msps, 1.8V ADC, DDR LVDS Outputs |
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