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參數(shù)資料
| 型號(hào)： | LTC2151CUP-14#PBF |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | ADC |
| 英文描述： | 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC40 |
| 封裝： | 6 X 6 MM, LEAD FREE, PLASTIC, QFN-40 |
| 文件頁數(shù)： | 28/32頁 |
| 文件大?。?/td> | 4005K |
| 代理商： | LTC2151CUP-14#PBF |
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5
21521014p
LTC2152-14/
LTC2151-14/LTC2150-14
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL DATA OUTPUTS
VOD
Differential Output Voltage
100Ω Differential Load, 3.5mA Mode
100Ω Differential Load, 1.75mA Mode
l
247
125
350
175
454
250
mV
VOS
Common Mode Output Voltage
100Ω Differential Load, 3.5mA Mode
100Ω Differential Load, 1.75mA Mode
l
1.125
1.250
1.375
V
RTERM
On-Chip Termination Resistance
Termination Enabled, OVDD = 1.8V
100
Ω
DIGITAL INPUTS AND OUTPUTS The
l
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 5)
TIMING CHARACTERISTICS The
l
denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER
CONDITIONS
LTC2152-14
LTC2151-14
LTC2150-14
UNITS
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
fS
Sampling Frequency
(Note 9)
l
10
250
10
210
10
170
MHz
tL
ENC Low Time (Note 8) Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
l
1.9
2
50
2.26
1.5
2.38
50
2.79
1.5
2.94
50
ns
tH
ENC High Time (Note 8) Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
l
1.9
2
50
2.26
1.5
2.38
50
2.79
1.5
2.94
50
ns
DIGITAL DATA OUTPUTS
SYMBOL PARAMETER
CONDITIONS
LTC215X-14
MIN
TYP
MAX
UNITS
tD
ENC to Data Delay
CL = 5pF
l
1.7
2
2.3
ns
tC
ENC to CLKOUT Delay
CL = 5pF
l
1.3
1.6
2
ns
tSKEW
DATA to CLKOUT Skew
tD – tC
l
0.3
0.4
0.55
ns
Pipeline Latency
5
Cycles
SPI Port Timing (Note 8)
tSCK
SCK Period
Write Mode, CSDO = 20pF
Readback Mode RPULLUP = 2k, CSDO = 20pF
40
250
ns
tS
CS to SCK Set-Up Time
l
5
ns
tH
SCK to CS Hold Time
l
5
ns
tDS
SDI Set-Up Time
l
5
ns
tDH
SDI Hold Time
l
5
ns
tDO
SCK Falling to SDO Valid
Readback Mode RPULLUP = 2k, CSDO = 20pF
l
125
ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND with GND and OGND
shorted (unless otherwise noted).
Note 3: When these pin voltages are taken below GND or above VDD, they
will be clamped by internal diodes. This product can handle input currents
of greater than 100mA below GND or above VDD without latchup.
Note 4: When these pin voltages are taken below GND they will be
clamped by internal diodes. When these pin voltages are taken above VDD
they will not be clamped by internal diodes. This product can handle input
currents of greater than 100mA below GND without latchup.
Note 5: VDD = OVDD = 1.8V, fSAMPLE = 250MHz (LTC2152),
210MHz (LTC2151), or 170MHz (LTC2150), LVDS outputs, differential
ENC+/ENC– = 2VP-P sine wave, input range = 1.5VP-P with differential
drive, unless otherwise noted.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
best fit straight line to the transfer curve. The deviation is measured from
the center of the quantization band.
Note 7: Offset error is the offset voltage measured from –0.5LSB when the
output code flickers between 00 0000 0000 0000 and 11 1111 1111 1111
in 2’s complement output mode.
Note 8: Guaranteed by design, not subject to test.
Note 9: Recommended operating conditions.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LTC2151IUP-14#PBF | 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC40 |
| LTC2151IUP-14#TRPBF | 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC40 |
| LTC2150IUP-14#PBF | 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC40 |
| LTC2150IUP-14#TRPBF | 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC40 |
| LTC2152CUP-14#PBF | 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC40 |
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| LTC2151IUJ-12#PBF | 制造商:Linear Technology 功能描述:IC ADC 12BIT 210MSPS 40QFN |
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