參數(shù)資料
型號： LTC2145IUP-14#PBF
廠商： LINEAR TECHNOLOGY CORP
元件分類： ADC
英文描述： 2-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64
封裝： 9 X 9 MM, LEAD FREE, PLASTIC, MO-220WNJR-5, QFN-64
文件頁數(shù)： 34/36頁
文件大?。?/td> 827K
代理商： LTC2145IUP-14#PBF
7
21454314f
LTC2145-14/
LTC2144-14/LTC2143-14
power requireMenTs The
l
denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 9)
SYMBOL PARAMETER
CONDITIONS
LTC2145-14
LTC2144-14
LTC2143-14
UNITS
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
CMOS Output Modes: Full Data Rate and Double Data Rate
VDD
Analog Supply Voltage (Note 10)
l
1.7
1.8
1.9
1.7
1.8
1.9
1.7
1.8
1.9
V
OVDD
Output Supply Voltage
(Note 10)
l
1.1
1.8
1.9
1.1
1.8
1.9
1.1
1.8
1.9
V
IVDD
Analog Supply Current DC Input
Sine Wave Input
l
105.2
105.9
116
82.8
83.3
92
62.8
63.2
70
mA
IOVDD
Digital Supply Current
Sine Wave Input, OVDD = 1.2V
8.5
7.1
5.4
mA
PDISS
Power Dissipation
DC Input
Sine Wave Input, OVDD = 1.2V
l
189
201
209
149
159
166
113
120
126
mW
LVDS Output Mode
VDD
Analog Supply Voltage (Note 10)
l
1.7
1.8
1.9
1.7
1.8
1.9
1.7
1.8
1.9
V
OVDD
Output Supply Voltage
(Note 10)
l
1.7
1.8
1.9
1.7
1.8
1.9
1.7
1.8
1.9
V
IVDD
Analog Supply Current Sine Input, 1.75mA Mode
Sine Input, 3.5mA Mode
l
107.3
108.7
123
84.7
86.1
97
64.6
66.1
75
mA
IOVDD
Digital Supply Current
(0VDD = 1.8V)
Sine Input, 1.75mA Mode
Sine Input, 3.5mA Mode
l
35.1
66.3
77
34.8
66
76
34.5
65.7
76
mA
PDISS
Power Dissipation
Sine Input, 1.75mA Mode
Sine Input, 3.5mA Mode
l
256
315
360
215
274
312
178
237
272
mW
All Output Modes
PSLEEP
Sleep Mode Power
1
mW
PNAP
Nap Mode Power
16
mW
PDIFFCLK Power Increase with Differential Encode Mode Enabled
(No increase for Nap or Sleep Modes)
20
mW
TiMing characTerisTics The
l
denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER
CONDITIONS
LTC2145-14
LTC2144-14
LTC2143-14
UNITS
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
fS
Sampling Frequency
(Note 10)
l
1
125
1
105
1
80
MHz
tL
ENC Low Time (Note 8) Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
l
3.8
2
4
500
4.52
2
4.76
500
5.93
2
6.25
500
ns
tH
ENC High Time (Note 8) Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
l
3.8
2
4
500
4.52
2
4.76
500
5.93
2
6.25
500
ns
tAP
Sample-and-Hold
Acquisition Delay Time
0
ns
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Digital Data Outputs (CMOS Modes: Full Data Rate and Double Data Rate)
tD
ENC to Data Delay
CL = 5pF (Note 8)
l
1.1
1.7
3.1
ns
tC
ENC to CLKOUT Delay
CL = 5pF (Note 8)
l
1
1.4
2.6
ns
tSKEW
DATA to CLKOUT Skew
tD – tC (Note 8)
l
0
0.3
0.6
ns
Pipeline Latency
Full Data Rate Mode
Double Data Rate Mode
6
6.5
Cycles
相關(guān)PDF資料
PDF描述
LTC2143CUP-14#PBF 2-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64
LTC2144CUP-14#PBF 2-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64
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