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參數(shù)資料
| 型號： | LTC1929I |
| 廠商： | Linear Technology Corporation |
| 元件分類： | 基準電壓源/電流源 |
| 英文描述： | Isolated Flyback Switching Regulator with 9V Output |
| 中文描述： | 隔離反激式開關(guān)穩(wěn)壓9V輸出 |
| 文件頁數(shù)： | 19/24頁 |
| 文件大?。?/td> | 233K |
| 代理商： | LTC1929I |
19
LTC1929
The duty factors when the peak RMS input current occurs
is at D = 0.25 and D = 0.75 according to Figure 4. Calculate
the worst-case required RMS current rating at the input
voltage that produces a duty cycle nearest to the peak.
C
IN
will require an RMS current rating of:
C requiredI
A
A
RMS
RMS
=
(
)
=
20
1 8
5 5
.
1
2
1
2
1 8
5 5
.
1
2
4 76
.
.
.
The output capacitor ripple current is calculated by using
the inductor ripple already calculated for each inductor
and multiplying by the factor obtained from Figure3 along
with the calculated duty factor. The output ripple in con-
tinuous mode will be highest at the maximum input
voltage since the duty factor is <50%. The maximum
output current ripple is:
I
V
fL
V
V
at
D F
I
V
)
μ
kHz
H
V
V
A
(
V
m
A
mV
COUT
OUT
OUT
IN
COUTMAX
OUTRIPPLE
RMS
=
=
(
=
=
(
)
)
=
1
0 33
0 66
.
33
1 8
.
310
2
1
1 8
5 5
.
0 54
.
0 97
20
0 97
.
19 4
.
% . .
.
.
.
An alternate calculation just uses the equation for output
ripple current at D = 1.8V/5.5 = 0.33:
I
V
(
kHz
H
A
(
V
m
A
mV
RIPPLE
OUTRIPPLE
RMS
=
(
)
μ
)
(
1 2 0 33
)
.
)
+
(
)
(
=
=
)
=
2 1 8
310
2
1 2 0 33 1 0 33
.
1
0 99
20
0 99
.
19 7
.
.
.
.
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC1929. These items are also illustrated graphically in
the layout diagram of Figure11. Check the following in
your layout:
1) Are the signal and power grounds segregated The
LTC1929 signal ground pin should return to the (–) plate
of C
OUT
separately. The power ground returns to the
sources of the bottom N-channel MOSFETs, anodes of the
Schottky diodes, and (–) plates of C
IN
, which should have
as short lead lengths as possible.
2) Does the LTC1929 V
OS+
pin connect to the (+) plate(s)
of C
OUT
Does the LTC1929 V
OS–
pin connect to the (–)
plate(s) of C
OUT
The resistive divider R1, R2 must be
connected between the V
DIFFOUT
and signal ground and
any feedforward capacitor across R1 should be as close as
possible to the LTC1929.
3) Are the SENSE
–
and SENSE
+
leads routed together with
minimum PC trace spacing The filter capacitors between
SENSE
+
and SENSE
–
pin pairs should be as close as
possible to the LTC1929. Ensure accurate current sensing
with Kelvin connections.
4) Do the (+) plates of C
IN
connect to the drains of the
topside MOSFETs as closely as possible This capacitor
provides the AC current to the MOSFETs. Keep the input
current path formed by the input capacitor, top and bottom
MOSFETs, and the Schottky diode on the same side of the
PC board in a tight loop to minimize conducted and
radiated EMI.
5) Is the INTV
CC
1
μ
F ceramic decoupling capacitor con-
nected closely between
INTV
CC
and the power ground pin
This capacitor carries the MOSFET driver peak currents. A
small value is used to allow placement immediately adja-
cent to the IC.
6) Keep the switching nodes, SW1 (SW2), away from
sensitive small-signal nodes. Ideally the switch nodes
should be placed at the furthest point from the LTC1929.
7) Use a low impedance source such as a logic gate to drive
the PLLIN pin and keep the lead as short as possible.
APPLICATIU
W
U
U
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