參數(shù)資料
型號(hào): LTC1929I
廠商: Linear Technology Corporation
元件分類(lèi): 基準(zhǔn)電壓源/電流源
英文描述: Isolated Flyback Switching Regulator with 9V Output
中文描述: 隔離反激式開(kāi)關(guān)穩(wěn)壓9V輸出
文件頁(yè)數(shù): 10/24頁(yè)
文件大?。?/td> 233K
代理商: LTC1929I
10
LTC1929
of the bottom MOSFET from turning on, storing charge
during the dead-time, and requiring a reverse recovery
period which would reduce efficiency. A 1A to 3A (depend-
ing on output current) Schottky diode is generally a good
compromise for both regions of operation due to the
relatively small average current. Larger diodes result in
additional transition losses due to their larger junction
capacitance.
C
IN
and C
OUT
Selection
In continuous mode, the source current of each top
N-channel MOSFET is a square wave of duty cycle V
OUT
/
V
IN
. A low ESR input capacitor sized for the maximum
RMS current must be used. The details of a close form
equation can be found in Application Note 77. Figure 4
shows the input capacitor ripple current for a 2-phase
configuration with the output voltage fixed and input
voltage varied. The input ripple current is normalized
against the DC output current. The graph can be used in
place of tedious calculations. The minimum input ripple
current can be achieved when the input voltage is twice the
output voltage. The minimum is not quite zero due to
inductor ripple current.
In the graph of Figure 4, the local maximum input RMS
capacitor currents are reached when:
V
V
k
OUT
IN
=
4
2
1
where k = 1, 2.
These worst-case conditions are commonly used for
design because even significant deviations do not offer
much relief. Note that capacitor manufacturer’s ripple
current ratings are often based on only 2000 hours of life.
This makes it advisable to further derate the capacitor, or
to choose a capacitor rated at a higher temperature than
required. Several capacitors may also be paralleled to
meet size or height requirements in the design. Always
consult the capacitor manufacturer if there is any ques-
tion.
It is important to note that the efficiency loss is propor-
tional to the input RMS current squaredand therefore a
2-stage implementation results in 75% less power loss
when compared to a single phase design. Battery/input
protection fuse resistance (if used), PC board trace and
connector resistance losses are also reduced by the re-
duction of the input ripple current in a 2-phase system. The
required amount of input capacitance is further reduced by
the factor, 2, due to the effective increase in the frequency
of the current pulses.
The selection of C
OUT
is driven by the required effective
series resistance (ESR). Typically once the ESR require-
ment has been met, the RMS current rating generally far
exceeds the I
RIPPLE(P-P)
requirements. The steady state
output ripple (
V
OUT
) is determined by:
V
I
ESR
fC
OUT
RIPPLE
OUT
+
1
16
Where f = operating frequency of each stage, C
OUT
=
output capacitance and
I
RIPPLE
= combined inductor
ripple currents.
The output ripple varies with input voltage since
I
L
is a
function of input voltage. The output ripple will be less than
50mV at max V
IN
with
I
L
= 0.4I
OUT(MAX)
/2 assuming:
C
OUT
required ESR < 4(R
SENSE
) and
C
OUT
> 1/(16f)(R
SENSE
)
The emergence of very low ESR capacitors in small,
surface mount packages makes very physically small
implementations possible. The ability to externally com-
pensate the switching regulator loop using the I
TH
pin(OPTI-
LOOP compensation) allows a much wider selection of
APPLICATIU
W
U
U
DUTY FACTOR (V
OUT
/V
IN
)
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
0.6
0.5
0.4
0.3
0.2
0.1
0
1929 F04
R
D
2-PHASE
1-PHASE
Figure 4. Normalized RMS Input Ripple Current vs
Duty Factor for 1 and 2 Output Stages
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