參數(shù)資料
型號(hào)： LTC1923EUH
廠商： LINEAR TECHNOLOGY CORP
元件分類(lèi)： 穩(wěn)壓器
英文描述： High Efficiency Thermoelectric Cooler Controller
中文描述： SWITCHING CONTROLLER, 270 kHz SWITCHING FREQ-MAX, PQCC32
封裝： 5 X 5 MM, PLASTIC, QFN-32
文件頁(yè)數(shù)： 16/28頁(yè)
文件大?。?/td> 452K
代理商： LTC1923EUH
16
LTC1923
1923f
If the external frequency (f
PLLIN
) is greater than the oscil-
lator frequency, current is sourced continuously out of the
PLLLPF pin. When the external frequency is less than the
oscillator frequency, current is sunk by the PLLLPF pin.
The loop filter components R
LP
, C
LP
and C
LP2
, smooth out
current pulses from the phase detector and provide a
stable input to the VCO. These components also determine
how fast the loop acquires lock. In most instances C
LP2
can be omitted, R
LP
can be set to 1k and C
LP
can be
selected to be 0.01
μ
F to 0.1
μ
F to stabilize the loop. Make
sure that the low side of filter components is tied to AGND
to keep unwanted switching noise from altering the perfor-
mance of the PLL.
Figure 9 illustrates three different ways to set the oscilla-
tor frequency. In Figure 9a, the oscillator is free running
with the frequency determined by R
T
and C
T
. In Figure 9b,
DIGITAL
PHASE
FREQUENCY
DETECTOR
V
DD
V
DD
PLLLPF
SDSYNCB
R
T
R
LP
C
LP
C
LP2
OSC
C
T
R
PLL
1923 F08
EXTERNAL
FREQUENCY
Figure 8. Phase-Locked Loop Block Diagram
the oscillator is slaved to an external clock. Figure 9c
illustrates how one LTC1923 can be used as a master to
synchronize other LTC1923s or additional devices requir-
ing synchronization. To implement this, determine the
values of R
T
and C
T
to obtain the desired free-running
oscillator frequency of the master by using the equation
given in the oscillator frequency section. Tie the master’s
PLLLPF pin to V
DD
and the SDSYNC pin to V
DD
through a
resistor R
PLL
as shown in Figure 9c. R
PLL
typically can be
set to 10k, but may need to be a lower value if higher
frequency operation is desired (above 250kHz). Set the
slave free-running frequencies to be 20% to 30% less
than this. The SDSYNC pin of the master will switch at its
free-running frequency (with approximately 50% duty
cycle), and this can be used to synchronize the other
devices.
OPERATIOU
PLLLPF
LTC1923
R
T
SDSYNC
NC
V
DD
C
T
R
T
C
T
1923 F09a
PLLLPF
LTC1923
R
T
SDSYNC
CLP2
RLP
CLP
CLKIN
C
T
R
T
C
T
1923 F09b
PLLLPF
LTC1923
R
T
SDSYNC
V
DD
C
T
R
T
C
T
PLLLPF
LTC1923
MASTER
SLAVE
R
T
1923 F09c
SDSYNC
CLP2
RLP
CLP
C
T
1.2 R
T
C
T
RPLL
(9a) Free Running
(9b) Slave Operation with External Clock—
Set Oscillator Frequency at 70% to 80% of External Clock
Figure 9. Oscillator Frequency Setup: a) Free Running b) Slaved Operation c) Master/Slave Operation
(9c) Master/Slave Operation—Set Oscillator Frequency of Slave at 70% to 80% of Master
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