參數(shù)資料
型號(hào): LTC1875EGN
廠商: LINEAR TECHNOLOGY CORP
元件分類: 穩(wěn)壓器
英文描述: 15mA Quiescent Current 1.5A Monolithic Synchronous Step-Down Regulator
中文描述: 3 A SWITCHING REGULATOR, 605 kHz SWITCHING FREQ-MAX, PDSO16
封裝: 0.150 INCH, PLASTIC, SSOP-16
文件頁數(shù): 6/20頁
文件大?。?/td> 257K
代理商: LTC1875EGN
6
LTC1875
1875f
PIU
SGND (Pin 1):
Signal Ground Pin.
RUN/SS (Pin 2):
Combination of Soft-Start and Run
Control Inputs. Forcing this pin below 0.7V shuts down the
device. In shutdown all functions are disabled and device
draws zero supply current. For the proper operation of the
part, force this pin above 2.5V. Do not leave this pin
floating. Soft-start can be accomplished by raising the
voltage on this pin gradually with an RC circuit.
V
FB
(Pin 3):
Feedback Pin. Receives the feedback voltage
from an external resistor divider across the output.
I
TH
(Pin 4):
Error Amplifier Compensation Point. The
current output increases with this control voltage. Nomi-
nal voltage range for this pin is 0.5V to 1.8V.
SWP1, SWP2 (Pins 5, 12):
Upper Switch Nodes. These
pins connect to the drains of the internal main PMOS
switches and should always be connected together
externally.
SWN1, SWN2 (Pins 6, 11):
Lower Switch Nodes. These
pins connect to the drains of the internal synchronous
NMOS switches and should always be connected together
externally.
PGND1, PGND2 (Pins 7, 10):
Power Ground Pins. Ground
pins for the internal drivers and switches. These pins
should always be tied together.
PV
IN1
, PV
IN2
(Pins 8, 9):
Power Supply Pins for the
Internal Drivers and Switches. These pins should always
be tied together.
SV
IN
(Pin 13):
Signal Power Supply Pin.
PGOOD (Pin 14):
Power Good Indicator Pin. Power good
is an open-drain logic output. The PGOOD pin is pulled to
ground when the voltage on the V
FB
pin is not within
±
7.5% of its nominally regulated potential. This pin re-
quires a pull-up resistor for power good indication. Power
good indication works in all modes of operation.
SYNC/MODE (Pin 15):
External Clock Synchronization
and Mode Select Input. To synchronize, apply an external
clock with a frequency between 350kHz and 750kHz. To
select Burst Mode operation, tie pin to SV
IN
. Grounding
this pin selects pulse skipping mode. Do not leave this pin
floating.
PLL_LPF (Pin 16):
Output of the Phase Detector and
Control Input of Oscillator. Connect a series RC lowpass
network from this pin to ground if externally synchronized.
If unused, this pin may be left open.
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