參數(shù)資料
型號: LTC1859CG
廠商: Linear Integrated Systems
英文描述: 8-Channel, 12-/14-/16-Bit, 100ksps SoftSpan A/D Converters with Shutdown
中文描述: 8通道,12-/14-/16-Bit,100ksps的具有關(guān)斷SoftSpan的A / D轉(zhuǎn)換器
文件頁數(shù): 5/20頁
文件大小: 265K
代理商: LTC1859CG
5
LTC1857/LTC1858/LTC1859
185789f
The
denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at T
A
= 25
°
C. (Note 5)
TI I G CHARACTERISTICS
U
W
SYMBOL
f
SAMPLE(MAX)
Maximum Sampling Frequency
PARAMETER
CONDITIONS
Through CH0 to CH7 Inputs
Through ADC
+
, ADC
Only
MIN
100
TYP
MAX
UNITS
kHz
kHz
166
4
t
CONV
t
ACQ
Conversion Time
Acquisition Time
5
4
μ
s
μ
s
μ
s
Through CH0 to CH7 Inputs
Through ADC
+
, ADC
Only
(Note 14)
See Test Circuits
See Test Circuits
1
f
SCK
t
r
t
f
t
1
t
2
t
3
t
4
t
5
t
6
t
7
SCK Frequency
SDO Rise Time
SDO Fall Time
CONVST High Time
CONVST to BUSY Delay
SCK Period
SCK High
SCK Low
Delay Time, SCK
to SDO Valid
Time from Previous SDO Data Remains
Valid After SCK
SDO Valid After RD
RD
to SCK Setup Time
SDI Setup Time Before SCK
SDI Hold Time After SCK
SDO Valid Before BUSY
Bus Relinquish Time
0
20
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
6
6
40
C
L
= 25pF, See Test Circuits
15
30
50
10
10
C
L
= 25pF, See Test Circuits
C
L
= 25pF, See Test Circuits
25
20
45
5
t
8
t
9
t
10
t
11
t
12
t
13
C
L
= 25pF, See Test Circuits
11
30
ns
ns
ns
ns
ns
ns
20
0
7
5
RD = Low, C
L
= 25pF, See Test Circuits
See Test Circuits
20
10
30
Note 1:
Absolute maximum ratings are those values beyond which the life
of a device may be impaired.
Note 2:
All voltage values are with respect to ground with DGND, AGND1,
AGND2 and AGND3 wired together unless otherwise noted.
Note 3:
When these pin voltages are taken below ground or above AV
DD
=
DV
DD
= OV
DD
= V
DD
, they will be clamped by internal diodes. This product
can handle currents of greater than 100mA below ground or above V
DD
without latchup.
Note 4:
When these pin voltages are taken below ground they will be
clamped by internal diodes. This product can handle currents of greater
than 100mA below ground without latchup. These pins are not clamped
to V
DD
.
Note 5:
V
DD
= 5V, f
SAMPLE
= 100kHz, t
r
= t
f
= 5ns unless otherwise
specified.
Note 6:
Linearity, offset and full-scale specifications apply for a single-
ended analog MUX input with respect to ground or ADC
+
with respect to
ADC
tied to ground.
Note 7:
Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual end points of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 8:
Bipolar zero error is the offset voltage measured from –0.5LSB
when the output code flickers between 0000 0000 0000 0000 and 1111
1111 1111 1111 for the LTC1859, between 00 0000 0000 0000 and 11
1111 1111 1111 for the LTC1858 and between 0000 0000 0000 and 1111
1111 1111 for the LTC1857. Unipolar zero error is the offset voltage
measured from 0.5LSB when the output codes flicker between 0000 0000
0000 0000 and 0000 0000 0000 0001 for the LTC1859, between 00 0000
0000 0000 and 00 0000 0000 0001 for the LTC1858 and between 0000
0000 0000 and 0000 0000 0001 for the LTC1857.
Note 9:
Guaranteed by design, not subject to test.
Note 10:
Recommended operating conditions.
Note 11:
Full-scale bipolar error is the worst case of –FS or +FS
untrimmed deviation from ideal first and last code transitions, divided by
the full-scale range, and includes the effect of offset error. For unipolar
full-scale error, the deviation of the last code transition from ideal, divided
by the full-scale range, and includes the effect of offset error.
Note 12:
All Specifications in dB are referred to a full-scale
±
10V input.
Note 13:
Recovers to specified performance after (2 FS) input
overvoltage.
Note 14:
t
6
of 45ns maximum allows f
SCK
up to 10MHz for rising capture
with 50% duty cycle and f
SCK
up to 20MHz for falling capture (with 5ns
setup time for the receiving logic).
Note 15:
The specification is referred to the
±
10V input range.
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