參數(shù)資料
型號(hào)： LTC1859CG
廠商： Linear Integrated Systems
英文描述： 8-Channel, 12-/14-/16-Bit, 100ksps SoftSpan A/D Converters with Shutdown
中文描述： 8通道，12-/14-/16-Bit，100ksps的具有關(guān)斷SoftSpan的A / D轉(zhuǎn)換器
文件頁(yè)數(shù)： 13/20頁(yè)
文件大小： 265K
代理商： LTC1859CG
13
LTC1857/LTC1858/LTC1859
185789f
APPLICATIU
11 1111 1111 1111 for the LTC1858 and between 0000
0000 0000 and 1111 1111 1111 for the LTC1857.
As mentioned earlier, the internal reference is factory
trimmed to 2.50V. To make sure that the reference buffer
gain is not compensating for trim errors in the reference,
REFCOMP is trimmed with an accurate external 2.5V ref-
erence applied to V
REF
. For unipolar inputs, an input volt-
age of FS – 1.5LSBs should be applied to the “+” input and
the appropriate reference adjusted until the output code
flickers between 1111 1111 1111 1110 and 1111 1111
1111 1111 for the LTC1859, between 11 1111 1111 1110
and 11 1111 1111 1111 for the LTC1858 and between
1111 1111 1110 and 1111 1111 1111 for the LTC1857.
For bipolar inputs, an input voltage of FS – 1.5LSBs should
be applied to the “+” input and the appropriate reference
adjusted until the output code flickers between 0111 1111
1111 1110 and 0111 1111 1111 1111 for the LTC1859,
between 01 1111 1111 1110 and 01 1111 1111 1111 for
the LTC1858 and between 0111 1111 1110 and 0111 1111
1111 for the LTC1857.
These adjustments as well as the factory trims affect all
channels. The channel-to-channel offset and gain error
matching are guaranteed by design to meet the specifica-
tions in the Converter Characteristics table.
W
U
U
Figure 5. LTC1859 Histogram for 4096 Conversions
DC PERFORMANCE
One way of measuring the transition noise associated
with a high resolution ADC is to use a technique where a
DC signal is applied to the input of the MUX and the
resulting output codes are collected over a large number
of conversions. For example in Figure 5 the distribution of
output code is shown for a DC input that has been digitized
4096 times. The distribution is Gaussian and the RMS
code transition is about 1LSB for the LTC1859.
DIGITAL INTERFACE
Internal Clock
The ADC has an internal clock that is trimmed to achieve
a typical conversion time of 4
μ
s. No external adjustments
are required and, with the maximum acquisition time of 4
μ
s,
throughput performance of 100ksps is assured.
3V Input/Output Compatible
The LTC1857/LTC1858/LTC1859 operate on a 5V supply,
which makes the devices easy to interface to 5V digital
systems. These devices can also interface to 3V digital
systems: the digital input pins (SCK, SDI, CONVST and
RD) of the LTC1857/LTC1858/LTC1859 recognize 3V or
5V inputs. The LTC1857/LTC1858/LTC1859 have a dedi-
cated output supply pin (OVP) that controls the output
swings of the digital output pins (SDO, BUSY) and allows
the part to interface to either 3V or 5V digital systems. The
output is two’s complement binary for bipolar mode and
offset binary for unipolar mode.
Timing and Control
Conversion start and data read are controlled by two
digital inputs: CONVST and RD. To start a conversion and
put the sample-and-hold into the hold mode bring CONVST
high for no less than 40ns. Once initiated it cannot be
restarted until the conversion is complete. Converter
status is indicated by the BUSY output and this is low while
the conversion is in progress.
Figures 6a and 6b show two different modes of operation
for the LTC1859. For the 12-bit LTC1857 and 14-bit
LTC1858, the last four and two bits of the SDO will output
zeros respectively. In mode 1 (Figure 6a), RD is tied low.
The rising edge of CONVST starts the conversion. The data
outputs are always enabled. The MSB of the data output is
available after the conversion. In mode 2 (Figure 6b),
CONVST and RD are tied together. The rising edge of the
CONVST signal starts the conversion. Data outputs are in
CODE
–4
–3
0
C
200
600
800
1000
2
3
1800
1859 F05
400
–2
–1
0
1
4
1200
1400
1600
相關(guān)PDF資料
PDF描述
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