參數(shù)資料
型號: LTC1773
廠商: Linear Technology Corporation
英文描述: Synchronous Step-Down Regulator Controller(同步步降穩(wěn)壓器)
中文描述: 同步降壓穩(wěn)壓控制器(同步步降穩(wěn)壓器)
文件頁數(shù): 12/20頁
文件大?。?/td> 274K
代理商: LTC1773
LTC1773
12
the zero frequency will be kept the same, thereby keeping
the phase shift the same in the most critical frequency
range of the feedback loop. The output voltage settling
behavior is related to the stability of the closed-loop
system and will demonstrate the actual overall supply
performance. For a detailed explanation of optimizing the
compensation components, including a review of control
loop theory, refer to Application Note 76.
A second, more severe transient is caused by switching in
loads with large (>1
μ
F) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with C
OUT
, causing a rapid drop in V
OUT
. No regulator can
deliver enough current to prevent this problem if the load
switch resistance is low and it is driven quickly. The only
solution is to limit the rise time of the switch drive so that
the load rise time is limited to approximately (25)(C
LOAD
).
Thus a 10
μ
F capacitor would require a 250
μ
s rise time,
limiting the charging current to about 200mA.
Minimum On-Time Considerations
Minimum on-time, t
ON(MIN)
, is the smallest amount of
time that the LTC1773 is capable of turning the top
MOSFET on and off again. It is determined by internal
timing delays and the gate charge required to turn on the
top MOSFET. The minimum on-time for the LTC1773 is
about 250ns. Low duty cycle and high frequency synchro-
nous applications may approach this minimum on-time
limit and care should be taken to ensure that:
t
V
f V
ON MIN
(
OUT
IN
)
<
If the duty cycle falls below what can be accommodated by
the minimum on-time, the LTC1773 will begin to skip
cycles. The output voltage will continue to be regulated,
but the ripple current and ripple voltage will increase.
If an application can operate close to the minimum on-
time limit, an inductor must be chosen that has low
enough inductance to provide sufficient ripple amplitude
to meet the minimum on-time requirement. As a general
rule, keep the inductor ripple current equal or greater than
30% of the I
OUT(MAX)
at V
IN(MAX).
APPLICATIO
S I
N
FOR
ATIO
U
Checking Transient Response
The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, V
OUT
immediately shifts by an amount
equal to (
I
LOAD
)(ESR), where ESR is the effective series
resistance of C
OUT
.
I
LOAD
also begins to charge or dis-
charge C
OUT
, which generates a feedback error signal. The
regulator loop then returns V
OUT
to its steady-state value.
During this recovery time, V
OUT
can be monitored for
overshoot or ringing. OPTI-LOOP compensation allows
the transient response to be optimized over a wide range
of output capacitance and ESR values. The availability of
the I
TH
pin not only allows optimization of control loop
behavior but also provides a DC coupled and an AC filtered
closed-loop response test point. The DC step, rise time
and settling at this test point reflects the closed loop
response. Assuming a predominantly second order sys-
tem, phase margin and/or damping factor can be esti-
mated using the percentage of overshoot seen at this pin.
The bandwidth can also be estimated by examining the
rise time at the pin. The I
TH
external components shown in
the Figure 1 circuit will provide an adequate starting point
for most applications.
The I
TH
series R
C
-C
C
filter sets the dominant pole-zero
loop compensation. The values can be modified slightly
(from 0.5 to 2 times their suggested values) to optimize
transient response once the final PC layout is done and the
particular output capacitor type and value have been
determined. The output capacitors need to be decided
upon because the various types and values determine the
loop feedback factor gain and phase. An output current
pulse of 20% to 100% of full load current having a rise time
of 1
μ
s to 10
μ
s will produce output voltage and I
TH
pin
waveforms that will give a sense of the overall loop
stability without breaking the feedback loop. The initial
output voltage step may not be within the bandwidth of the
feedback loop, so the standard second order overshoot/
DC ratio cannot be used to determine phase margin. The
gain of the loop will be increased by increasing R
C
, and the
bandwidth of the loop will be increased by decreasing C
C
.
If R
C
is increased by the same factor that C
C
is decreased,
W
U
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