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參數(shù)資料
| 型號： | LTC1773 |
| 廠商： | Linear Technology Corporation |
| 英文描述： | Synchronous Step-Down Regulator Controller(同步步降穩(wěn)壓器) |
| 中文描述： | 同步降壓穩(wěn)壓控制器（同步步降穩(wěn)壓器） |
| 文件頁數(shù)： | 11/20頁 |
| 文件大?。?/td> | 274K |
| 代理商： | LTC1773 |
LTC1773
11
drawn from the auxiliary windings without regard to the
primary output load.
The secondary output voltage is set by the turns ratio of the
transformer in conjunction with a pair of external resistors
returned to the SYNC/FCB pin as shown in Figure 5. The
secondary regulated voltage, V
SEC
, in Figure 5 is given by:
V
N
V
V
V
R
R
SEC
OUT
DIODE
+
(
)
>
+
1
0 8
.
1
4
3
where N is the turns ratio of the transformer and V
OUT
is
the main output voltage sensed by V
FB
.
power MOSFET gate charge current, I
2
R losses, and
topside MOSFET transition losses.
1. The V
IN
quiescent current is due to the DC bias current
as given in the electrical characteristics, it excludes
MOSFET driver and control currents. V
IN
current results
in a small loss which increases with V
IN
.
2. The external MOSFET gate charge current results from
switching the gate capacitance of the external power
MOSFET switches. Each time the gate is switched from
high to low to high again, a packet of charge dQ moves
from V
IN
to ground. The resulting dQ/dt is the current
out of V
IN
; it is typically larger than the DC bias current.
In continuous mode, I
GATECHG
= f(Q
T
+ Q
B
) where Q
T
and Q
B
are the gate charges of the external main and
synchronous switches. Both the DC bias and gate
charge losses are proportional to V
IN
and thus their
effects will be more pronounced at higher supply volt-
ages.
3. I
2
R losses are calculated from the resistances of the
external R
SENSE
, the external power MOSFETs (R
SW
)
and the external inductor (R
L
). In continuous mode, the
average output current flowing through inductor L is
“chopped” between the main switch and the synchro-
nous switch. Thus, the series resistance looking into
the SW pin from L is a function of both top and bottom
MOSFET R
DS(ON)
and the duty cycle (DC), as follows:
R
SW
= (R
DS(ON)TOP
+R
SENSE
) DC + R
DS(ON)BOT
(1 – DC)
The R
DS(ON)
for both the top and bottom MOSFETs can
be obtained from the MOSFET manufactures’s
datasheets. Thus, to obtain I
2
R losses, simply add R
SW
and R
L
together and multiply their sum by the square of
the average output current.
4. Transition losses apply to the topside MOSFET and
increase when operating at high input voltages and
higher operating frequencies. Transition losses can be
estimated from:
Transition Loss = 2(V
IN
)
2
I
O(MAX)
C
RSS
(f)
Other losses including C
IN
and C
OUT
ESR dissipative
losses, and inductor core losses, generally account for
less than 2% total additional loss.
APPLICATIO
S I
N
FOR
ATIO
U
W
U
Efficiency Considerations
The efficiency of a switching regulator is equal to the
output power divided by the input power times 100%. It is
often useful to analyze individual losses to determine what
is limiting the efficiency and which change would produce
the most improvement. Efficiency can be expressed as:
Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percentage
of input power.
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
losses in LTC1773 circuits: V
IN
quiescent current, external
Figure 5. Secondary Output Loop Connection
LTC1773
+
+
R4
R3
1
μ
F
V
OUT
V
SEC
C
OUT
L1
1:N
SYNC/FCB
BG
SW
TG
1773 F05
V
IN
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