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參數(shù)資料
| 型號： | LTC1740IG |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 6/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC SMPL 14BIT 6MSPS 36-SSOP |
| 標準包裝： | 37 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 6M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 300mW |
| 電壓電源： | 雙 ± |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 36-SSOP（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 36-SSOP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 2 個單端，雙極；1 個差分，雙極 |
14
LTC1740
1740f
As with all fast ADCs, the noise performance of the
LTC1740 is sensitive to clock jitter when high speed inputs
are present. The SNR performance of an ADC when the
performance is limited by jitter is given by:
SNR = – 20log (2
πfINtJ)dB
where fIN is the frequency of an input sine wave and tJ is
the root-mean-square jitter due to the clock, the analog
input and the A/D aperture jitter. To minimize clock jitter,
use a clean clock source such as a crystal oscillator, treat
the clock signals as sensitive analog traces and use
dedicated packages with good supply bypassing for any
clock drivers.
Board Layout
To obtain the best performance from the LTC1740, a
printed circuit board with a ground plane is required.
Layout for the printed circuit board should ensure that
digital and analog signal lines are separated as much as
possible. In particular, care should be taken not to run any
digital track alongside an analog signal track.
An analog ground plane separate from the logic system
ground should be placed under and around the ADC.
Pins 6, 7, 10, 31, 34 (GND), Pins 11, 28 (OGND) and all
other analog grounds should be connected to this ground
plane. In single supply mode, Pins 29, 30 (VSS) should
also be connected to this ground plane. All bypass capaci-
tors for the LTC1740 should also be connected to this
ground plane (Figure 12). The digital system ground
DIGITAL
SYSTEM
–AIN
+AIN
1
2
1000pF
1740 F12
LTC1740
ANALOG GROUND PLANE
1
F
34
32
GND
VDD
33
VDD
31
GND
1
F
19
OVDD
1
F
5
VREF
1
F
3
VCM
11
OGND
10
GND
7
GND
6
GND
1
F
8
VDD
9
VDD
1
F
29
VSS
30
VSS
28
OGND
+
–
ANALOG
INPUT
CIRCUITRY
Figure 12. Power Supply Grounding
should be connected to the analog ground plane at only
one point, near the OGND pin (Pin 28).
The analog ground plane should be as close to the ADC as
possible. Care should be taken to avoid making holes in the
analog ground plane under and around the part. To ac-
complish this, we recommend placing vias for power and
signal traces outside the area containing the part and the
decoupling capacitors (Figure 13).
Supply Bypassing
High quality, low series resistance ceramic 1
F capacitors
should be used at the VDD pins, VCM and VREF. If VSS is
connected to – 5V it should also be bypassed to ground
with 1
F. In single supply operation VSSshouldbeshorted
to the ground plane as close to the part as possible. OVDD
requires a 1
F decoupling capacitor to ground. Surface
mount capacitors such as the AVX 0805ZC105KAT pro-
vide excellent bypassing in a small board space. The traces
connecting the pins and the bypass capacitors must be
kept short and should be made as wide as possible.
APPLICATIO S I FOR ATIO
WU
UU
AVOID BREAKING GROUND PLANE
IN THIS AREA
PLACE NON-GROUND
VIAS AWAY FROM
GROUND PLANE AND
BYPASS CAPACITORS
ANALOG
GROUND
PLANE
BYPASS
CAPACITOR
1740 F13
LTC1740
Figure 13. Cross Section of the LTC1740 Printed Circuit Board
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