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參數(shù)資料
| 型號： | LTC1735IS-1#TRPBF |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 3 A SWITCHING CONTROLLER, 550 kHz SWITCHING FREQ-MAX, PDSO16 |
| 封裝： | 0.150 INCH, PLASTIC, SO-16 |
| 文件頁數(shù)： | 14/28頁 |
| 文件大小： | 343K |
| 代理商： | LTC1735IS-1#TRPBF |
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21
LTC1735-1
APPLICATIO S I FOR ATIO
WU
U
decreases the output voltage starts at a level lower than
nominal so the output voltage can have more overshoot
and stay within the specified voltage range. Less output
capacitance is required when voltage positioning is used
because more voltage variation is allowed on the output
capacitors.
Active voltage positioning can be implemented using the
OPTI-LOOP architecture of the LTC1735-1 and two resis-
tors connected to the ITH pin. An input voltage offset is
introduced when the error amplifier has to drive a resistive
load. This offset voltage is limited to
±30mV at the input
of the error amplifier. The resulting change in output
voltage is the product of input offset voltage and the
feedback voltage divider ratio.
Figure 8 shows a CPU-core-voltage regulator with active
voltage positioning. Resistors R1 and R5 force the input
voltage offset that adjusts the output voltage according to
the load current level. To select values for R1 and R5, first
determine the amount of output deregulation allowed. The
actual specification for a typical microprocessor allows
the output to vary
±0.112V. The LTC1735-1 reference
accuracy is
±1%. Using 1% tolerance resistors, the total
feedback divider accuracy is about 1% because both
feedback resistors are close to the same value. The result-
ing setpoint accuracy is
±2% so the output transient
voltage cannot exceed
±0.082V. For VOUT = 1.5V, the
maximum output voltage change controlled by the ITH pin
would be:
=
±
=±
V
Input Offset Voltage V
V
mV
OSENSE
OUT
REF
. .
.
003
1 5
08
56
With optimum resistor values at the ITH pin, the output
voltage will swing from 1.55V at minimum load to 1.44V
at full load. At this output voltage, active voltage position-
ing provides an additional
±56mV to the allowable tran-
sient voltage on the output capacitors, a 68% improvement
over the
±82mV allowed without active voltage
positioning.
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
COSC
RUN/SS
ITH
PGOOD
SENSE –
SENSE+
VOSENSE
SGND
TG
BOOST
SW
VIN
INTVCC
BG
PGND
EXTVCC
U1
LTC1735-1
C2
0.1
F
C8
0.22
F
C4
100pF
C6
47pF
C3
100pF
R2
100k
R1
27k
PGOOD
R6
0.003
GND
VOUT
1.5V
15A
VIN
7.5V TO
24V
GND
C5
1000pF
C1
39pF
+
C10
4.7
F
10V
C9
1
F
C11
330pF
C19
1
F
+
C15 TO
C18
180
F
4V
C7
0.1
F
Q1
FDS6680A
Q2, Q3
FDS6680A
×2
C9, C19: TAIYO YUDEN JMK107BJ105
C10: KEMET T494A475M010AS
C12 TO C14: TAIYO YUDEN GMK325F106
C15 TO C18: PANASONIC EEFUE0G181R
D1: CENTRAL SEMI CMDSH-3
D2: MOTOROLA MBRS340
L1: PANASONIC ETQP6F1R0SA
Q1 TO Q3: FAIRCHILD FDS6680A
R5: IRC LRF2512-01-R003-J
U1: LINEAR TECHNOLOGY LTC1735CS-1
1735-1 F08
D1
CMDSH-3
5V (OPTIONAL)
R7
10k
R8
11.5k
D2
MBRS340
C12 TO C14
10
F
35V
L1
1
H
R5 100k
R4 100k
R3 680k
Figure 8. CPU-Core-Voltage Regulator with Active Voltage Positioning
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