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參數(shù)資料
| 型號： | LTC1662IN8 |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 16/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 10BIT DUAL ULT LPWR 8DIP |
| 標(biāo)準(zhǔn)包裝： | 50 |
| 設(shè)置時間： | 400µs |
| 位數(shù)： | 10 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 260µW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 8-DIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 8-PDIP |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 2 電壓，單極 |
| 采樣率（每秒）： | * |
LTC1662
9
1662fa
operation
Table 1. DAC Control Functions
CONTROL
INPUT REGISTER
STATUS
DAC REGISTER
STATUS
POWER-DOWN STATUS
(SLEEP/WAKE)
COMMENTS
A3 A2 A1 A0
0
No Change
No Update
No Change
No Operation. Power-Down Status Unchanged
(Part Stays In Wake or Sleep Mode)
0
1
Load DAC A
No Update
No Change
Load Input Register A with Data. DAC Outputs Unchanged.
Power-Down Status Unchanged
0
1
0
Load DAC B
No Update
No Change
Load Input Register B with Data. DAC Outputs Unchanged.
Power-Down Status Unchanged
1
0
No Change
Update Outputs
Wake
Load Both DAC Regs with Existing Contents of Input Regs.
Outputs Update. Part Wakes Up
1
0
1
Load DAC A
Update Outputs
Wake
Load Input Reg A. Load DAC Regs with New Contents of
Input Reg A and Existing Contents of Reg B. Outputs Update.
Part Wakes Up
1
0
1
0
Load DAC B
Update Outputs
Wake
Load Input Reg B. Load DAC Regs with Existing Contents of
Input Reg A and New Contents of Reg B. Outputs Update.
Part Wakes Up
1
0
1
No Change
No Update
Wake
Part Wakes Up. Input and DAC Regs Unchanged.
DAC Outputs Reflect Existing Contents of DAC Regs
1
0
No Change
No Update
Sleep
Part Goes to Sleep. Input and DAC Regs Unchanged.
DAC Outputs Set to High Impedance State
1
Load DACs A, B
with Same
10-Bit Code
Update Outputs
Wake
Load Both Input Regs. Load Both DAC Regs with New
Contents of Input Regs. Outputs Update. Part Wakes Up
Note: All control codes other than those shown are undefined and not subject to test.
Transfer Function
The transfer function for the LTC1662 is:
VOUT(IDEAL) =
k
1024
VREF
where k is the decimal equivalent of the binary DAC input
code D9-D0 and VREF is the voltage at REF (Pin 4).
Power-On Reset
The LTC1662 actively clears the outputs to zero-scale
when power is first applied, making system initialization
consistent and repeatable.
Power Supply Sequencing
The voltage at REF (Pin 4) should be kept within the range
–0.3V ≤ VREF ≤ VCC + 0.3V (see the Absolute Maximum
Ratings). Particular care should be taken during power
supplyturn-onandturn-offsequences,whenthevoltageat
VCC (Pin 6) is in transition. If it is not possible to sequence
the supplies, clamp the voltage at REF by connecting a
SchottkydiodebetweenPin4(anode)andPin6(cathode).
Serial Interface
See Table 2. The 16-bit input word consists of the 4-bit
controlcode,the10-bitinputcodeandtwodon’t-carebits.
Table 2. LTC1662 Input Word
A3 A2 A1
Control Code
A0 D9 D8 D7 D6 D5 D4 D3 D2 D1
X1 X0
D0
Input Code
Input Word
Don’t
Care
Aftertheinputwordisloadedintotheregister(seeFigure1),
it is internally converted from serial to parallel format. The
parallel 10-bit-wide input code data path is then buffered
by two latch registers.
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