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參數(shù)資料
| 型號： | LTC1662IN8 |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 14/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 10BIT DUAL ULT LPWR 8DIP |
| 標(biāo)準(zhǔn)包裝： | 50 |
| 設(shè)置時(shí)間： | 400µs |
| 位數(shù)： | 10 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 260µW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 8-DIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 8-PDIP |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 2 電壓，單極 |
| 采樣率（每秒）： | * |
LTC1662
7
1662fa
pin Functions
CS/LD (Pin 1): Serial Interface Chip Select/Load Input.
When CS/LD is low, SCK is enabled for shifting data on
SDI into the register. When CS/LD is pulled high, SCK is
disabledandtheoperation(s)specifiedinthecontrolcode,
A3-A0, is (are) performed. CMOS and TTL compatible.
SCK (Pin 2): Serial Interface Clock Input. CMOS and TTL
compatible.
SDI (Pin 3): Serial Interface Data Input. Input word data
on the SDI pin is shifted into the 16-bit register on the
rising edge of SCK. CMOS and TTL compatible.
REF (Pin 4): Reference Voltage Input. 0V ≤ VREF ≤ VCC.
VOUTA,VOUTB(Pin8,Pin5):DACAnalogVoltageOutputs.
The output range is
0
≤ VOUTA,VOUTB ≤ VREF
1023
1024
VCC (Pin 6): Supply Voltage Input. 2.7V ≤ VCC ≤ 5.5V.
GND (Pin 7): System Ground.
DeFinitions
Differential Nonlinearity (DNL): The difference between
the measured change and the ideal 1LSB change for any
two adjacent codes. The DNL error between any two codes
is calculated as follows:
DNL = (VOUT – LSB)/LSB
where VOUT is the measured voltage difference between
two adjacent codes.
Full-Scale Error (FSE): The deviation of the actual full-
scale voltage from ideal. FSE includes the effects of offset
and gain errors (see Figure 2).
Gain Error (GE): The deviation from the slope of the ideal
DAC transfer function, expressed in LSBs at full-scale.
Integral Nonlinearity (INL): The deviation from a straight
line passing through the endpoints of the DAC transfer
curve (endpoint INL). Because the output cannot go
below zero, the linearity is measured between full-scale
and the lowest code which guarantees the output will be
greater than zero. The INL error at a given input code is
calculated as follows:
INL = [VOUT – VOS – (VFS – VOS)(code/1023)]/LSB
where VOUT is the output voltage of the DAC measured at
the given input code.
Least Significant Bit (LSB): The ideal voltage difference
between two successive codes.
LSB = VREF/1024
Resolution (n): Defines the number of DAC output states
(2n) that divide the full-scale range. Resolution does not
imply linearity.
Voltage Offset Error (VOS): Nominally, the voltage at the
output when the DAC is loaded with all zeros. A single
supply DAC can have a true negative offset, but the output
cannot go below zero (see Figure 2).
For this reason, single supply DAC offset is measured at
the lowest code that guarantees the output will be greater
than zero.
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