參數(shù)資料
型號： LTC1661IMS8#PBF
廠商： Linear Technology
文件頁數(shù)： 14/14頁
文件大小： 0K
描述： IC D/A CONV 10BIT MICRPWR 8-MSOP
標(biāo)準(zhǔn)包裝： 50
設(shè)置時(shí)間： 30µs
位數(shù)： 10
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 2
電壓電源： 單電源
功率耗散（最大）： 260µW
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 8-TSSOP，8-MSOP（0.118"，3.00mm 寬）
供應(yīng)商設(shè)備封裝： 8-MSOP
包裝： 管件
輸出數(shù)目和類型： 2 電壓，單極
采樣率（每秒）： *
LTC1661
9
1661fa
OPERATION
Table 2. DAC Control Functions
CONTROL
INPUT REGISTER
STATUS
DAC REGISTER
STATUS
POWER-DOWN STATUS
(SLEEP/WAKE)
COMMENTS
A3 A2 A1 A0
0
No Change
No Update
No Change
No Operation. Power-Down Status Unchanged
(Part Stays in Wake or Sleep Mode)
0
1
Load DAC A
No Update
No Change
Load Input Register A with Data. DAC Outputs
Unchanged. Power-Down Status Unchanged
0
1
0
Load DAC B
No Update
No Change
Load Input Register B with Data. DAC Outputs
Unchanged. Power-Down Status Unchanged
0
1
Reserved
0
1
0
Reserved
0
1
0
1
Reserved
0
1
0
Reserved
0
1
Reserved
1
0
No Change
Update Outputs
Wake
Load Both DAC Regs with Existing Contents of Input
Regs. Outputs Update. Part Wakes Up
1
0
1
Load DAC A
Update Outputs
Wake
Load Input Reg A. Load DAC Regs with New Contents
of Input Reg A and Existing Contents of Reg B. Outputs
Update. Part Wakes Up
1
0
1
0
Load DAC B
Update Outputs
Wake
Load Input Reg B. Load DAC Regs with Existing
Contents of Input Reg A and New Contents of Reg B.
Outputs Update. Part Wakes Up
1
0
1
Reserved
1
0
Reserved
1
0
1
No Change
No Update
Wake
Part Wakes Up. Input and DAC Regs Unchanged. DAC
Outputs Reflect Existing Contents of DAC Regs
1
0
No Change
No Update
Sleep
Part Goes to Sleep. Input and DAC Regs Unchanged.
DAC Outputs Set to High Impedance State
1
Load DACs A, B with
Same 10-Bit Code
Update Outputs
Wake
Load Both Input Regs. Load Both DAC Regs with New
Contents of Input Regs. Outputs Update. Part Wakes Up
DIN
SCK
CS/LD
A3
A2
INPUT CODE
DON’T CARE
A1
A0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X1
X0
1661 F01
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
(SCK ENABLED)
(LTC1661
RESPONDS)
CONTROL CODE
INPUT WORD W0
Figure 1. Register Loading Sequence
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