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參數(shù)資料
| 型號： | MC100ES6014EJ |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 1/8頁 |
| 文件大小： | 0K |
| 描述： | IC CLOCK BUFFER MUX 2:5 20-TSSOP |
| 標準包裝： | 74 |
| 系列： | 100ES |
| 類型： | 扇出緩沖器（分配），多路復(fù)用器 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:5 |
| 差分 - 輸入:輸出： | 是/是 |
| 輸入： | ECL，HSTL，LVDS，PECL |
| 輸出： | ECL，PECL |
| 頻率 - 最大： | 2GHz |
| 電源電壓： | ±2.375 V ~ 3.8 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-TSSOP |
| 包裝： | 管件 |
| 其它名稱： | 800-2227 MC100ES6014EJ-ND |
DATA SHEET
2.5 V/3.3 V 1:5 Differential
ECL/PECL/HSTL/LVDS Clock Driver
MC100ES6014
MC100ES6014 REVISION 4 DECEMBER 18, 2012
1
2012 Integrated Device Technology, Inc.
The MC100ES6014 is a low skew 1-to-5 differential driver, designed with clock
distribution in mind, accepting two clock sources into an input multiplexer. The
ECL/PECL input signals can be either differential or single-ended (if the VBB
output is used). HSTL and LVDS inputs can be used when the ES6014 is
operating under PECL conditions.
The ES6014 specifically guarantees low output-to-output skew. Optimal
design, layout, and processing minimize skew within a device and from device to
device.
To ensure that the tight skew specification is realized, both sides of any
differential output need to be terminated identically into 50
even if only one
output is being used. If an output pair is unused, both outputs may be left open
(unterminated) without affecting skew.
The common enable (EN) is synchronous, outputs are enabled/disabled in the
LOW state. This avoids a runt clock pulse when the device is enabled/disabled
as can happen with an asynchronous control. The internal flip flop is clocked on
the falling edge of the input clock; therefore, all associated specification limits are
referenced to the negative edge of the clock input.
The MC100ES6014, as with most other ECL devices, can be operated from a
positive VCC supply in PECL mode. This allows the ES6014 to be used for high
performance clock distribution in +3.3 V or +2.5 V systems. Single ended CLK
input pin operation is limited to a VCC 3.0 V in PECL mode, or VEE –3.0 V in
ECL mode. Designers can take advantage of the ES6014's performance to
distribute low skew clocks across the backplane or the board.
Features
25 ps Within Device Skew
400 ps Typical Propagation Delay
Maximum Frequency > 2 GHz Typical
The 100 Series Contains Temperature Compensation
PECL and HSTL Mode: VCC = 2.375 V to 3.8 V with VEE = 0 V
ECL Mode: VCC = 0 V with VEE = –2.375 V to –3.8 V
LVDS and HSTL Input Compatible
Open Input Default State
20-Lead Pb-Free Package Available
Replacement part: ICS853S014I
MC100ES6014
ORDERING INFORMATION
Device
Package
MC100ES6014EJ
TSSOP-20 (Pb-Free)
MC100ES6014EJR2
TSSOP-20 (Pb-Free)
DT SUFFIX
20-LEAD TSSOP PACKAGE
CASE 948E-03
EJ SUFFIX
20-LEAD TSSOP PACKAGE
Pb-FREE PACKAGE
CASE 948E-03
Product Discontinuance Notice – Last Time Buy Expires on (12/3/2013)
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| MC100ES6014EJR2 | 功能描述:時鐘驅(qū)動器及分配 FSL 1-5 Differential LVPECL Fanout Buffe RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| MC100ES6017DW | 制造商:Integrated Device Technology Inc 功能描述:LINE RCVR 4RX 20SOIC - Rail/Tube |
| MC100ES6017DWR2 | 制造商:Integrated Device Technology Inc 功能描述:LINE RCVR 4RX 20SOIC - Tape and Reel |
| MC100ES6017EG | 功能描述:時鐘驅(qū)動器及分配 FSL LVPECL Quad Diff Receiver RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| MC100ES6017EGR2 | 功能描述:時鐘緩沖器 FSL LVPECL Quad Diff Receiver RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
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