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參數(shù)資料
| 型號： | LTC1654I |
| 廠商： | Linear Technology Corporation |
| 英文描述： | Dual LinCMOS(TM) Timer 14-SOIC |
| 中文描述： | 雙14位軌至軌DAC，采用16引線SSOP封裝 |
| 文件頁數(shù)： | 4/12頁 |
| 文件大?。?/td> | 154K |
| 代理商： | LTC1654I |
4
LTC1654
X
1
/X
1/2
B, X
1
/X
1/2
A (Pins 1, 8):
The Gain of 1 or Gain of
1/2 Pin. When this pin is tied to V
OUT
, the output will swing
up to REFHI/2 and when this pin is tied to REFLO, the
output will swing up to REFHI. These pins should not be
left floating.
CLR (Pin 2):
The Asynchronous Clear Input.
SCK (Pin 3):
The TTL Level Input for the Serial Interface
Clock.
SDI (Pin 4):
The TTL Level Input for the Serial Interface
Data. Data on the SDI pin is latched into the shift register
on the rising edge of the serial clock. The LTC1654 re-
quires a 24-bit word. The first 8 bits are control/address
followed by 16 data bits. The last two of the 16 data bits are
don’t cares. If daisy-chaining is desired, then a 32-bit data
word can be used with the first 8 being don’t cares and the
following 24 bits as above.
CS/LD (Pin 5):
The TTL Level Input for the Serial Interface
Enable and Load Control. When CS/LD is low, the SCK
signal is enabled, so the data can be clocked in. When
CS/LD is pulled high, the control/address bits are
decoded.
DGND/AGND (Pins 6, 12):
Digital and Analog Grounds.
SDO (Pin 7):
The output of the shift register that becomes
valid on the rising edge of the serial clock.
V
OUT A/B
(Pins 9, 15):
The Buffered DAC Outputs.
REFHI A/B (Pins 10, 14):
The Reference High Inputs of the
LTC1654. There is a gain of 1 from this pin to the output
in a gain of 1 configuration. In a gain of 1/2 configuration,
there is a gain of 1/2 from this pin to V
OUT
.
REFLO A/B (Pins 11, 13):
The Reference Low Inputs of the
LTC1654.
V
CC
(Pin 16):
The Positive Supply Input. 2.7V
≤
V
CC
≤
5.5V.
Requires a 0.1
μ
F bypass capacitor to ground.
1654 TD01
t
1
t
4
t
3
t
5
B0
C3
C3
X
X
X
CURRENT WORD
X
X
X
X
X
X
SCK
CS/LD
SDI
SDO
t
2
t
8
t
6
t
7
t
9
(PREVIOUS
WORD)
TIW
W
Note 1:
Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2:
Nonlinearity is defined from code 50 to code 16383 (full scale).
See Applications Information.
Note 3:
100pF Load Capacitor
Note 4:
DAC switched between code 200 and code 16383.
Note 5:
Digital inputs at 0V or V
CC
.
Note 6:
Guaranteed by design.
Note 7:
V
OUT
can only swing from (GND +
V
OS
) to (V
CC
–
V
OS
)
when output is unloaded. See Applications Information.
Note 8:
CS/LD = 0, V
OUT
= 4.096 and data is being clocked in.
PIU
ELECTRICAL CHARACTERISTICS
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