參數(shù)資料
型號(hào): LTC1654I
廠商: Linear Technology Corporation
英文描述: Dual LinCMOS(TM) Timer 14-SOIC
中文描述: 雙14位軌至軌DAC,采用16引線SSOP封裝
文件頁(yè)數(shù): 1/12頁(yè)
文件大小: 154K
代理商: LTC1654I
1
LTC1654
Dual 14-Bit Rail-to-Rail DAC
in 16-Lead SSOP Package
April 2000
I
14-Bit Monotonic Over Temperature
I
Individually Programmable Speed/Power:
3.5
μ
s Settling Time at 750
μ
A
8
μ
s Settling Time at 450
μ
A
I
Maximum Update Rate: 0.9MHz
I
Smallest Dual 14-Bit DAC: 16-Lead Narrow
SSOP Package
I
Buffered True Rail-to-Rail Voltage Outputs
I
3V to 5V Single Supply Operation
I
User Selectable Gain
I
Power-On Reset and Clear Function
I
Schmitt Trigger On Clock Input Allows Direct
Optocoupler Interface
The LTC
1654 is a dual, rail-to-rail voltage output, 14-bit
digital-to-analog converter (DAC). It is available in a
16-lead narrow SSOP package, making it the smallest dual
14-bit DAC available. It includes output buffer amplifiers
and a flexible serial interface.
The LTC1654 has REFHI pins for each DAC that can be
driven up to V
CC
. The output will swing from 0V to V
CC
in
gain of 1 configuration or V
CC
/2 in gain of 1/2 configura-
tion. It operates from a single 2.7V to 5.5V supply.
The LTC1654 has two programmable speeds: a FAST and
SLOW mode with
±
1LSB settling times of 3.5
μ
s or 8
μ
s
respectively and supply currents of 750
μ
A and 450
μ
A in
the two modes. The LTC1654 also has shutdown capabil-
ity, power-on reset and clear function to 0V.
I
Digital Calibration
I
Industrial Process Control
I
Automatic Test Equipment
I
Offset/Gain Adjustment
, LTC and LT are registered trademarks of Linear Technology Corporation.
DAC B
1654 BD
V
OUT B
REFHI B
V
OUT A
X
/X
B
REFHI A
+
POWER-ON
RESET
DAC A
REFLO A
REFLO B
X
1
/X
1/2
A
+
INPUT
LATCH
CONTROL
LOGIC
CS/LD
SCK
SDO
CLR
SDI
INPUT
LATCH
DAC
REGISTER
32-BIT
SHIFT
REGISTER
DAC
REGISTER
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
Final Electrical Specifications
FEATURES
DESCRIPTIOU
APPLICATIU
BLOCK DIAGRA
相關(guān)PDF資料
PDF描述
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