參數(shù)資料
型號: LTC1654CGN
廠商: LINEAR TECHNOLOGY CORP
元件分類: DAC
英文描述: Dual LinCMOS(TM) Timer 14-SOIC
中文描述: SERIAL INPUT LOADING, 8.5 us SETTLING TIME, 14-BIT DAC, PDSO16
封裝: 0.150 INCH, PLASTIC, SSOP-16
文件頁數(shù): 7/12頁
文件大?。?/td> 154K
代理商: LTC1654CGN
7
LTC1654
Power Down
Each DAC can also be independently powered down to less
than 5
μ
A/DAC of supply current. The reference pin also
goes into a high impedance state when the DAC is powered
down and the reference current will drop to below 0.1
μ
A.
The amplifiers’ output stage is also three-stated but the
OPERATIO
U
Table 1.
CONTROL
C3
0
0
0
0
0
0
C2
0
0
0
0
1
1
C1
0
0
1
1
0
0
C0
0
1
0
1
0
1
Load Input Register n
Update (Power-Up) DAC Register n
Load Input Register n, Update (Power-Up) All
Load and Update n
Power Down n
Fast n (Speed States are Maintained Even If DAC is
Put in Power-Down Mode)
Slow n (Default State is Slow When Supplies are
Powered Up)
Reserved (Do Not Use)
Reserved (Do Not Use)
Reserved (Do Not Use)
Reserved (Do Not Use)
Reserved (Do Not Use)
Reserved (Do Not Use)
Reserved (Do Not Use)
Reserved (Do Not Use)
No Operation
0
1
1
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
V
OUT
pins still have the internal gain-setting resistors
connected to them resulting in an effective resistance from
V
OUT
to REFLO. This resistance is typically 90k when the
X
1
/X
1/2
pin is tied to V
OUT
and 36k when X
1
/X
1/2
is tied to
REFLO. Because of this resistance, V
OUT
will go to V
REFLO
when the DAC is powered down and V
OUT
is unloaded.
ADDRESS (n)
A3
A2
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
A1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
DAC A
DAC B
Reserved (Do Not Use)
Reserved (Do Not Use)
Reserved (Do Not Use)
Reserved (Do Not Use)
Reserved (Do Not Use)
Reserved (Do Not Use)
Reserved (Do Not Use)
Reserved (Do Not Use)
Reserved (Do Not Use)
Reserved (Do Not Use)
Reserved (Do Not Use)
Reserved (Do Not Use)
Reserved (Do Not Use)
Both DACs
INPUT WORD
C3
CONTROL
ADDRESS
DATA (14 + 2 DUMMY LSBs)
C2
C1
C0 A3 A2 A1
A0
D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
X
1654 TABLE
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