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參數(shù)資料
| 型號： | LTC1647-1IS8#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 13/22頁 |
| 文件大?。?/td> | 239K |
| 描述： | IC CONTROLLR HOTSWAP DUAL 8-SOIC |
| 標準包裝： | 2,500 |
| 類型： | 熱交換控制器 |
| 應(yīng)用： | 通用 |
| 內(nèi)部開關(guān)： | 無 |
| 電源電壓： | 2.7 V ~ 16.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOIC |
| 包裝： | 帶卷 (TR) |
LTC1647-1/
LTC1647-2/LTC1647-3
13
1647fa
Autoretry
The LTC1647-2 and LTC1647-3 are designed to allow an
automatic reset of the electronic circuit breaker after a
fault condition occurs. This is accomplished by pulling
the ON/FAULT (LTC1647-2) pin or the ON and FAULT pins
tied together (LTC1647-3) high through a resistor, R3, as
shown in Figure 7. An autoretry sequence begins if a fault
occurs. If the circuit breaker trips, FAULT pulls the ON
pin low. After a t
RESET
interval elapses, FAULT resets and
R3 pulls the ON pin up. C3 delays GATE turn-on until the
voltage at the ON pin exceeds V
IH
. The delay time is
t
DELAY
= R3"C3"ln[1(V
IH
V
OL
)/(V
ON
V
OL
)]
GATE ramps up at 10糀/C1 until Q1 conducts. If V
OUT
is
still shorted to GND, the cycle repeats. The ramp interval
is about t
RAMP
= V
TH
"C1/10糀 where V
TH
is the threshold
voltage of the external MOSFET.
Hot Circuit Insertion
When circuit boards are inserted into a live backplane or
a device bay, the supply bypass capacitors on the board
can draw huge transient currents from the backplane or
the device bay power bus as they charge up. The transient
currents can damage the connector pins and glitch the
system supply, causing other boards in the system to
reset or malfunction.
The LTC1647 is designed to turn two positive supplies on
and off in a controlled manner, allowing boards to be safely
inserted or removed from a live backplane or device bay.
The LTC1647 can be located before or after the connector
as shown in Figure 8. A staggered PCB connector can
sequence pin conections when plugging and unplugging
circuit boards. Alternatively, the control signal can be
generated by processor control.
Ringing
Good engineering practice calls for bypassing the supply
rail of any circuit. Bypass capacitors are often placed at
the supply connection of every active device, in addition
to one or more large value bulk bypass capacitors per
supply rail. If power is connected abruptly, the bypass
APPLICATIONS INFORMATION
capacitors slow the rate of rise of voltage and heavily
damp any parasitic resonance of lead or trace inductance
working against the supply bypass capacitors.
The opposite is true for LTC1647 Hot Swap circuits on a
daughterboard. In most cases, on the powered side of the
MOSFET switch (V
CC
) there is no supply bypass capacitor
present. An abrupt connection, produced by plugging a
board into a backplane connector, results in a fast rising
edge applied to the V
CC
line of the LTC1647.
No bulk capacitance is present to slow the rate of rise and
heavily damp the parasitic resonance. Instead, the fast edge
shock excites a resonant circuit formed by a combination
of wiring harness, backplane and circuit board parasitic
inductances and MOSFET capacitance. In theory, the peak
voltage should rise to 2X the input supply, but in practice
the peak can reach 2.5X, owing to the effects of voltage
dependent MOSFET capacitance.
The absolute maximum V
CC
potential for the LTC1647 is
17V; any circuit with an input of more than 6.8V should be
scrutinized for ringing. A well-bypassed backplane should
not escape suspicion: circuit board trace inductances
of as little as 10nH can produce sufficient ringing to
overvoltage V
CC
.
Check ringing with a fast storage oscilloscope (such as a
LECROY 9314AL DSO) by attaching coax or a probe to V
CC
and GND, then repeatedly inserting the circuit board into
the backplane. Figures 9a and 9b show typical results in a
12V application with different V
CC
lead lengths. The peak
amplitude reaches 22V , breaking down the ESD protection
diode in the process.
There are two methods for eliminating ringing: clipping
and snubbing. A transient voltage suppressor is an
effec tive means of limiting peak voltage to a safe level.
Figure 10 shows the effect of adding an ON Semiconduc-
tor, 1SMA12CAT3, on the waveform of Figure 9.
Figures 11a and 11b show the effects of snubbing with
different RC networks. The capacitor value is chosen as
10X to 100X the MOSFET C
OSS
under bias and R is selected
for best damping1?to 50?depending on the value of
parasitic inductance.
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