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參數(shù)資料
| 型號： | LTC1647-1IS8#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 12/22頁 |
| 文件大?。?/td> | 239K |
| 描述： | IC CONTROLLR HOTSWAP DUAL 8-SOIC |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | 熱交換控制器 |
| 應(yīng)用： | 通用 |
| 內(nèi)部開關(guān)： | 無 |
| 電源電壓： | 2.7 V ~ 16.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOIC |
| 包裝： | 帶卷 (TR) |
LTC1647-1/
LTC1647-2/LTC1647-3
12
1647fa
APPLICATIONS INFORMATION
V
CC
+ ?/DIV>
V
GATE
V
CC
V
CC
V
ON
C
LOAD
DISCHARGES
RAMP-DOWN
SLOPE = 50糀/C1
RAMP-UP
SLOPE = 10糀/C1
V
OUT
V
GATE
0V
0V
1647-1/2/3 F05
V
CC
+ ?/DIV>
V
GATE
V
CC
V
CC
V
CC
V
LKO
V
LKO
V
LKH
C
LOAD
DISCHARGES
V
CC
UNPLUGGED
OUT OF UVLO
INTO UVLO
FAST RAMP-DOWN
AT UNDERVOLTAGE
LOCKOUT
V
GATE
DROOP
DUE TO V
CC
RAMP-UP
SLOPE = 10糀/C1
V
OUT
V
GATE
0V
0V
1647-1/2/3 F06
Figure 5. Supply Turn-On/Off with ON
Figure 6. Supply Turn-On/Off with V
CC
SENSE
8
6
ON/FAULT
V
CC
V
OUT
FAULT
ON
(5V LOGIC)
2
GND
4
GATE
LTC1647-2
C1
10nF
R2
10?/DIV>
R1
0.01?/DIV>
Q1
IRF7413
C
LOAD
+
V
CC
1
R3
15k
C3
0.1糉
t
RESET
t
DELAY
t
RAMP
V
CC
V
SENSE
V
GATE
V
FAULT
1647-1/2/3 F07
an input supply greater than 10V at V
CC1
or V
CC2
, a 24V
Zener is recommended between the corresponding GATE1
or GATE2 pin and GND as shown in Figures 1 and 4.
The R
DS(ON)
of the external pass transistor must be low to
make V
DS
a small percentage of V
CC
. At V
CC
= 3.3V , V
DS
+ V
CB
= 0.1V yields 3% error at maximum load current.
This restricts the choice of MOSFETs to very low R
DS(ON)
.
At higher V
CC
voltages, the R
DS(ON)
requirement can be
relaxed. MOSFET package dissipation (P
D
and T
J
) may
restrict the value of R
DS(ON)
.
Power Supply Ramping
V
OUT
is controlled by placing MOSFET Q1 in the power
path (Figure 1). R1 provides load current fault detection
and R2 prevents MOSFET high frequency oscillation. By
ramping the gate of the pass transistor at a controlled
rate (dV/dt = 10糀/C1), the transient surge current
(I = C
LOAD
"dV/dt = 10糀"C
LOAD
/C1) drawn from the main
backplane is limited to a safe value when the board is
inserted into the connector.
When power is first applied to V
CC
, the GATE pin pulls low.
A low-to-high transition at the ON pin initiates GATE ramp-
up. The rising dV/dt of GATE is set by 10糀/C1 (Figure 5),
where C1 is the total external capacitance between
GATE and GND. The ramp-up time for V
OUT
is equal to
t = (V
CC
"C1)/10糀.
A high-to-low transition at the ON pin initiates a GATE
ramp-down at a slope of 50糀/C1. This rate is usually
adequate as the supply bypass capacitors take time to
discharge through the load.
If the ON pin is connected to V
CC
, or is pulled high before
V
CC
is first applied, GATE is held low until V
CC
rises above
the undervoltage lockout threshold, V
LKO
(Figure 6). Once
the threshold is exceeded, GATE ramps at a controlled rate
of 10糀/C1. When the power supply is disconnected, the
body diode of Q1 holds V
CC
about 700mV below V
OUT
.
The GATE voltage droops at a rate determined by V
CC
. If
V
CC
drops below V
LKO
V
LKH
, the LTC1647 enters UVLO
and GATE pulls down to GND.
Figure 7. Autoretry Sequence
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