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參數(shù)資料
| 型號： | LTC1421ISW-2.5#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 13/24頁 |
| 文件大小： | 329K |
| 描述： | IC CONTROLLER HOT SWAP 24-SOIC |
| 標準包裝： | 32 |
| 類型： | 熱交換控制器 |
| 應用： | 通用 |
| 內部開關： | 無 |
| 電源電壓： | 3 V ~ 12 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-SOIC（0.295"，7.50mm 寬） |
| 供應商設備封裝： | 24-SOIC |
| 包裝： | 管件 |
13
LTC1421/LTC1421-2.5
APPLICATIONS INFORMATION
U
U
U
signal is pulled high, turning off the switches. After the
board supply voltage ramps up and RESET goes high,
DISABLE will pull low enabling the switches.
Board Insertion Timing
When the board is inserted, GND pin makes contact first,
followed by V
CCHI
and V
CCLO
(Figure 14, time point 1).
DISABLE is immediately pulled high, so the data bus
switch is disabled. At the same time CON1 and CON2 make
contact and are shorted to ground on the host side (time
point 3). Since most boards need to be rocked back and
forth to get them in place, there is a period of time when
only one side of the connector is making contact. CON1
and CON2 should be located at opposite ends of the
connector.
Figure 14. Board Insertion Timing
can usually be prevented by using logic that does not
include the clamping diodes such as the QSI 74FCTT
family from Quality Semiconductor, or by using a data bus
switch such as the 10-bit QS3384 QuickSwitch also from
Quality Semiconductor (Tel: 408-450-8000). The
QuickSwitch bus switch contains an N-channel placed in
series with the data bus. The switch is turned off when the
board is inserted and then enabled after the power is
stable. The switch inputs and outputs do not have a
parasitic diode back to V
CC
and have very low capacitance.
The LTC1421 is designed to work directly with the
QuickSwitch bus switch as shown in Figure 13.
The DISABLE signal is connected to the enable pins of the
QS3384, and each switch is placed in series with a data
bus signal. When the board is inserted, the DISABLE
V
CCLO
1
2
3
4
5
6
V
CCHI
DISABLE
CON1
CON2
CPON
GATEHI
PWRGD
V
TH1
1421 F14
V
OUTHI
V
OUTLO
GATELO
RESET
FAULT
POR
200ms
20ms
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