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參數(shù)資料
| 型號： | LTC1412CG#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 5/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC A/D CONV 12BIT SAMPLNG 28SSOP |
| 標準包裝： | 47 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 3M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 220mW |
| 電壓電源： | 雙 ± |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SSOP（0.209"，5.30mm 寬） |
| 供應商設備封裝： | 28-SSOP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 2 個單端，雙極；1 個差分，雙極 |
| 產(chǎn)品目錄頁面： | 1346 (CN2011-ZH PDF) |
13
LTC1412
APPLICATIONS INFORMATION
WU
U
plane to the power supply should be low impedance.
Digital circuitry grounds must be connected to the digital
supply common. Low impedance analog and digital power
supply lines are essential to low noise operation of the
ADC. The traces connecting the pins and bypass capaci-
tors must be kept short and should be made as wide as
possible.
The LTC1412 has differential inputs to minimize noise
coupling. Common mode noise on the AIN+ and AIN– leads
will be rejected by the input CMRR. The AIN– input can be
used as a ground sense for the AIN+ input; the LTC1412
will hold and convert the difference voltage between AIN+
and AIN–. The leads to AIN+ (Pin 1) and AIN– (Pin 2) should
be kept as short as possible. In applications where this is
not possible, the AIN+ and AIN– traces should be run side
by side to equalize coupling.
Supply Bypassing
High quality, low series resistance ceramic, 10
F bypass
capacitors should be used at the VDD and REFCOMP pins.
Surface mount ceramic capacitors such as Murata
GRM235Y5V106Z016 provide excellent bypassing in a
small board space. Alternatively 10
F tantalum capacitors
in parallel with 0.1
F ceramic capacitors can be used.
Bypass capacitors must be located as close to the pins as
possible. The traces connecting the pins and the bypass
capacitors must be kept short and should be made as wide
as possible.
Example Layout
Figures 13a, 13b, 13c and 13d show the schematic and
layout of an evaluation board. The layout demonstrates the
proper use of decoupling capacitors and ground plane
with a two layer printed circuit board.
Figure 12. Power Supply Grounding Practice
LTC1412
AIN
+
ANALOG INPUT
AIN
–
VREF
REFCOMP
AGND
1412 F11b
1
2
3
R4
100
R2
50k
R3
24k
–5V
R6
24k
R1
50k
R5
47k
4
5
10
F
Figure 11b. Offset and Full-Scale Adjust Circuit
– 0.61mV (i.e., – 0.5LSB) at AIN+ and adjust the offset at
the AIN– input until the output code flickers between 0000
0000 0000 and 1111 1111 1111. For full-scale adjust-
ment, an input voltage of 2.49817V (FS/2 – 1.5LSBs) is
applied to AIN+ and R2 is adjusted until the output code
flickers between 0111 1111 1110 and 0111 1111 1111.
Board Layout and Bypassing
To obtain the best performance from the LTC1412, a
printed circuit board with ground plane is required. Layout
for the printed circuit board should ensure that digital and
analog signal lines are separated as much as possible. In
particular, care should be taken not to run any digital line
alongside an analog signal line.
An analog ground plane separate from the logic system
ground should be established under and around the ADC.
Pin 5 (AGND), Pins 19 and 14 (DGND) and Pin 22 (OGND)
and all other analog grounds should be connected to this
single analog ground point. The REFCOMP bypass capaci-
tor and the DVDD bypass capacitor should also be con-
nected to this analog ground plane, see Figure 12. All
analog circuitry grounds should be terminated to this
analog ground plane. The ground return from the ground
1412 F12
AIN
+
AGND
REFCOMP
VSS
AVDD
LTC1412
DIGITAL
SYSTEM
ANALOG
INPUT
CIRCUITRY
5
4
2
26
OVDD DVDD
21
20, 27
28
OGND
DGND
14, 19
22
POWER
SUPPLY
GROUND
1
0.1
F
AIN
–
0.1
F0.1F
10
F
ANALOG GROUND PLANE
+
–
+
10
F
10
F
+
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