FUNCTIONAL BLOCK DIAGRA " />
參數(shù)資料
型號(hào): LTC1406CGN#PBF
廠商: Linear Technology
文件頁(yè)數(shù): 14/16頁(yè)
文件大?。?/td> 0K
描述: IC A/D CONV 8BIT SAMPLING 24SSOP
標(biāo)準(zhǔn)包裝: 55
位數(shù): 8
采樣率(每秒): 20M
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 225mW
電壓電源: 模擬和數(shù)字,雙 ±
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 24-SSOP(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 24-SSOP
包裝: 管件
輸入數(shù)目和類型: 2 個(gè)單端,雙極;1 個(gè)差分,雙極
7
LTC1406
FUNCTIONAL BLOCK DIAGRA
UU
W
APPLICATIONS INFORMATION
WU
U
Conversion Details
The LTC1406 uses an internal sample-and-hold circuit and
a pipeline quantizing architecture to convert an analog
signal to an 8-bit parallel output. With CLK high the input
switches are closed and the analog input will be acquired
on the input sampling capacitors CS (see Figure 1).
On the falling edge of CLK the input switches open, captur-
ing the input signal. The sampling capacitors are then
shorted together and the charge is transferred to the hold
TRACK-AND-
HOLD AMP
DIGITAL
DATA
8-BIT
PIPELINE
ADC
2.5k
AVDD
VBIAS
VREF
OVDD
DVDD
OGND
AGND
SHDN
1.95k
2.2V
OUTPUT
DRIVERS
OF/UF
D7
D6
D5
D4
D3
D2
D1
D0
1406 BD
CLOCK
CIRCUITRY
CLK
AIN
+
7
8
94
10
3
5
6
1
23
2
11
12
22
21
20
19
18
17
16
15
24
AIN
DGND
+
CH
CLK
1406 F01
CLK
TO NEXT STAGE
CLK
AIN
+
AIN
CH
CS
CLK
Figure 1. Input Sample-and-Hold Amplifier
capacitors CH resulting in a differential DC voltage on the
output of the track-and-hold amplifier that is proportional
to the input signal. This differential voltage is fed into a
comparator that determines the most significant bit and
subtracts the result. The residue is then amplified by two
and passed to the next stage via a similar sample-and-hold
circuit. This continues down the eight pipeline stages. The
comparator outputs are then combined in a digital error
correction circuit. The 8-bit word is available at the output,
five clock cycles after the sampling edge.
Dynamic Performance
The LTC1406 has excellent wideband sampling capability.
The sample-and-hold amplifier has a small-signal input
bandwidth of 250MHz allowing the ADC to undersample
input signals with frequencies well beyond the converter’s
Nyquist frequency. FFT (Fast Fourier Transform) test tech-
niques are used to test the ADC’s frequency response,
distortion and noise at the rated throughput. By applying
a low distortion sine wave and analyzing the digital output
using an FFT algorithm, the ADC’s spectral content can be
examined for frequencies outside the fundamental. Figure
2 shows a typical LTC1406 FFT plot.
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