參數(shù)資料
型號(hào): LTC1297DCN8
廠商: Linear Technology
文件頁(yè)數(shù): 21/24頁(yè)
文件大?。?/td> 0K
描述: IC DATA ACQ SYSTEM 12BIT 8-DIP
標(biāo)準(zhǔn)包裝: 50
類型: 數(shù)據(jù)采集系統(tǒng)(DAS)
分辨率(位): 12 b
采樣率(每秒): 60k
數(shù)據(jù)接口: 串行,并聯(lián)
電壓電源: 單電源
電源電壓: 5V
工作溫度: 0°C ~ 70°C
安裝類型: 通孔
封裝/外殼: 8-DIP(0.300",7.62mm)
供應(yīng)商設(shè)備封裝: 8-PDIP
包裝: 管件
產(chǎn)品目錄頁(yè)面: 1346 (CN2011-ZH PDF)
6
LTC1292/LTC1297
12927fb
CC
HARA TERISTICS
UW
A
TYPICALPERFOR
CE
100
0.2
MAXIMUM
CLK
FREQUENCY*
(MHz)
0.4
0.6
0.8
1.0
1k
10k
100k
LTC1292/7G13
0
VCC = 5V
VREF = 5V
CLK = 1MHz
RSOURCE– ()
+
+IN
–IN
+VIN
RSOURCE
Maximum Filter Resistor vs
Cycle Time
PI FU CTIO S
U
UU
* MAXIMUM CLK FREQUENCY REPRESENTS THE
CLK FREQUENCY AT WHICH A 0.1LSB SHIFT IN
THE ERROR AT ANY CODE TRANSITION FROM ITS
1MHz VALUE IS FIRST DETECTED.
** MAXIMUM RFILTER REPRESENTS THE FILTER
RESISTOR VALUE AT WHICH A 0.1LSB CHANGE IN
FULL SCALE ERROR FROM ITS VALUE AT
RFILTER = 0 IS FIRST DETECTED.
CYCLE TIME (
s)
10
MAXIMUM
R
FILTER
**
(
)
100
1k
10k
10
1k
10k
LTC1292/7 G14
1
100
+
+VIN
CFILTER ≥1F
RFILTER
Maximum Clock Rate vs
Source Resistance
RSOURCE+ ()
100
1
S
&
H
AQUISITION
TIME
TO
0.02%
(
s)
10
100
1000
10000
LTC1292/7 G15
+
+VIN
RSOURCE
VREF = 5V
VCC = 5V
TA = 25°C
0V TO 5V INPUT STEP
Sample-and-Hold Acquisition
Time vs Source Resistance
Input Channel Leakage Current vs
Temperature
AMBIENT TEMPERATURE (
°C)
–50
0
INPUT
CHANNEL
LEAKAGE
CURRENT
(nA)
100
300
400
500
1000
700
–10
30
50
130
LTC1292/7 G16
200
800
900
600
–30
10
70
90 110
ON CHANNEL
OFF CHANNEL
GUARANTEED
Noise Error vs Reference Voltage
REFERENCE VOLTAGE (V)
0
PEAK-TO-PEAK
NOISE
ERROR
(LSB)
0.25
0.75
1.00
1.25
2
4
5
2.25
0.50
13
1.50
1.75
2.00
LTC1292/7 G17
LTC1292/LTC1297
NOISE = 200
VP-P
CS (Pin 1): Chip Select Input. A logic low on this input
enables the LTC1292/LTC1297. Power shutdown is acti-
vated on the LTC1297 when CS is brought high.
+IN, –IN (Pin 2, 3): Analog Inputs. These inputs must be
free of noise with respect to GND.
GND (Pin 4): Analog Ground. GND should be tied directly
to an analog ground plane.
VREF (Pin 5): Reference Input. The reference input defines
the span of the A/D converter and must be kept free of
noise with respect to GND.
DOUT (Pin 6): Digital Data Output. The A/D conversion
result is shifted out of this output.
CLK (Pin 7): Shift Clock. This clock synchronizes the serial
data transfer.
VCC (Pin 8):Positive Supply. This supply must be kept free
of noise and ripple by bypassing directly to the analog
ground plane.
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