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參數(shù)資料
| 型號： | LTC1287CIJ |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | ADC |
| 英文描述： | 3V Single Chip 12-Bit Data Acquisition System |
| 中文描述： | 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, CDIP8 |
| 封裝： | CERAMIC, DIP-8 |
| 文件頁數(shù)： | 11/16頁 |
| 文件大?。?/td> | 324K |
| 代理商： | LTC1287CIJ |
LTC1287
11
D
OUT
CLK
B11
HI-Z
B10
LTC1287 F8c
CS
1ST BIT TEST (–) INPUT MUST
SETTLE DURING THIS TIME
t
WHCS
t
SMPL
(+) INPUT MUST SETTLE DURING THIS TIME
(+) INPUT
(–) INPUT
U
S
A
O
PPLICATI
U
U
Figure 9. Adequate Settling of Op Amp Driving Analog Input
(see Figures 8a, 8b and 8c). Again the “+” and “–” input
sampling times can be extended as described above to
accommodate slower op amps. For single supply low
voltage application the LT1006, LT1013 and LT1014 can
be made to settle well even with the minimum settling
windows of 6
μ
s (“+” input) and 2
μ
s (“–” input) which
occur at the maximum clock rates (CLK = 500kHz).
Figures 9 and 10 show examples of adequate and poor op
amp settling. The LT1077, LT1078 or LT1079 can be used
here to reduce power consumption. Placing an RC network
at the output of the op amps will inprove the settling
response and also reduce the broadband noise.
effectively “held” by the sample and hold and will not affect
the conversion result. It is critical that the “–” input voltage
be free of noise and settle completely during the first CLK
cycle of the conversion. Minimizing R
SOURCE
– and C2 will
improve settling time. If large “–” input source resistance
must be used the time can be extended by using a slower
CLK frequency. At the maximum CLK frequency of 500kHz,
R
SOURCE
– < 200
and C2 < 20pF will provide adequate
settling.
Input Op Amps
When driving the analog inputs with an op amp it is
important that the op amp settles within the allowed time
HORIZONTAL: 500ns/DIV
Figure 8c. Setup Time (t
SUCS
) is Not Met
V
V
HORIZONTAL: 20
μ
s/DIV
Figure 10. Poor Op Amp Settling Can Cause A/D Errors
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