AIN (Pin 1): Analog Input. 0V to 2.5V (Unipolar), ±1.25V
參數(shù)資料
型號: LTC1282BCSW#PBF
廠商: Linear Technology
文件頁數(shù): 24/24頁
文件大?。?/td> 0K
描述: IC A/D CONV SAMPLING W/REF24SOIC
標(biāo)準(zhǔn)包裝: 32
位數(shù): 12
采樣率(每秒): 140k
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 24mW
電壓電源: 雙 ±
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 24-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 24-SOIC
包裝: 管件
輸入數(shù)目和類型: 1 個單端,單極;1 個單端,雙極
9
LTC1282
PI FU CTIO S
UU
U
AIN (Pin 1): Analog Input. 0V to 2.5V (Unipolar), ±1.25V
(Bipolar).
VREF (Pin 2): +1.20V Reference Output. Bypass to
AGND (10
F tantalum in parallel with 0.1F ceramic).
AGND (Pin 3): Analog Ground.
D11-D4 (Pins 4 to 11): Three-State Data Outputs. D11
is the Most Significant Bit.
DGND (Pin 12): Digital Ground.
D3/11-D0/8 (Pins 13 to 16): Three-State Data Outputs.
NC (Pins 17 and 18): No Connection.
HBEN (Pin 19): High Byte Enable Input. This pin is used
to multiplex the internal 12-bit conversion result into
the lower bit outputs (D7 and D0/8). See Table 1. HBEN
also disables conversion start when HIGH.
RD (Pin 20): READ Input. This active low signal starts a
conversion when CS and HBEN are low. RD also enables
the output drivers when CS is low.
CS (Pin 21): The CHIP SELECT Input must be low for the
ADC to recognize RD and HBEN inputs.
BUSY (Pin 22): The BUSY Output shows the converter
status. It is low when a conversion is in progress.
VSS (Pin 23): Bipolar Mode — Negative Supply, – 3V.
Bypass to AGND with 0.1
F ceramic.
Unipolar Mode — Tie to DGND.
VDD (Pin 24): Positive Supply, 3V. Bypass to AGND (10F
tantalum in parallel with 0.1
F ceramic).
Table 1. Data Bus Output, CS and RD = LOW
Pin 4
Pin 5
Pin 6
Pin 7
Pin 8
Pin 9
Pin 10
Pin 11
Pin 13
Pin 14
Pin 15
Pin 16
MNEMONIC*
D11
D10
D9
D8
D7
D6
D5
D4
D3/11
D2/10
D1/9
D0/8
HBEN = LOW
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
HBEN = HIGH
DB11
DB10
DB9
DB8
LOW
DB11
DB10
DB9
DB8
*D11...D0/8 are the ADC data output pins.
DB11...DB0 are the 12-bit conversion results, DB11 is the MSB.
TEST CIRCUITS
Load Circuits for Access Time
Load Circuits for Output Float Delay
3k
CL
DBN
(A) Hi-Z TO VOH, (t3)
AND VOL TO VOH, (t6)
(B) Hi-Z TO VOL, (t3)
AND VOH TO VOL, (t6)
DBN
3k
5V
1282 TC01
DGND
3k
10pF
DBN
(A) VOH TO Hi-Z
(B) VOL TO Hi-Z
DBN
3k
5V
1282 TC02
DGND
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