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參數(shù)資料
| 型號(hào)： | LTC1264-7CN |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 運(yùn)動(dòng)控制電子 |
| 英文描述： | Linear Phase, Group Delay Equalized, 8th Order Lowpass Filter |
| 中文描述： | SWITCHED CAPACITOR FILTER, BESSEL, LOWPASS, PDIP14 |
| 封裝： | 0.300 INCH, PLASTIC, DIP-14 |
| 文件頁數(shù)： | 9/12頁 |
| 文件大?。?/td> | 301K |
| 代理商： | LTC1264-7CN |
9
LTC1264-7
PI FU
Power Supply Pins (4, 12)
The V
+
(pin 4) and the V
–
(pin 12) should each be
bypassed with a 0.1
μ
F capacitor to an adequate analog
ground. The filter’s power supplies should be isolated
from other digital or high voltage analog supplies. A low
noise linear supply is recommended. Using a switching
power supply will lower the signal-to-noise ratio of the
filter. The supply during power-up should have a slew rate
less than 1V/
μ
s. When V
+
is applied before V
–
and V
–
is
allowed to go above ground, a signal diode should clamp
V
–
to prevent latch-up. Figures 2 and 3 show typical
connections for dual and single supply operation.
U
Clock Input Pin (11)
Any TTL or CMOS clock source with a square-wave output
and 50% duty cycle (
±
10%) is an adequate clock source
for the device. The power supply for the clock source
should not be the filter’s power supply. The analog ground
for the filter should be connected to clock’s ground at a
single point only. Table 7 shows the clock’s low and high
level threshold values for a dual or single supply operation.
A pulse generator can be used as a clock source provided
the high level ON time is greater than 0.1
μ
s. Sine waves are
not recommended for clock input frequencies less than
100kHz, since excessively slow clock rise or fall times
generate internal clock jitter (maximum clock rise or fall
time
≤
1
μ
s). The clock signal should be routed from the
right side of the IC package and perpendicular to it to avoid
coupling to any input or output analog signal path. A 200
resistor between clock source and pin 11 will slow down
the rise and fall times of the clock to further reduce charge
coupling (Figures 2 and 3).
Table 7. Clock Source High and Low Threshold Levels
POWER SUPPLY
Dual Supply =
±
7.5V
Dual Supply =
±
5V
Dual Supply =
±
2.5V
Single Supply = 12V
Single Supply = 5V
HIGH LEVEL
≥
2.18V
≥
1.45V
≥
0.73V
≥
7.80V
≥
1.45V
LOW LEVEL
≤
0.5V
≤
0.5V
≤
–2.0V
≤
6.5V
≤
0.5V
age is recommended. The analog ground plane should be
connected to any digital ground at a single point. For dual
supply operation, pin 3 should be connected to the analog
ground plane. For single supply operation pin 3 should be
biased at 1/2 supply and should be bypassed to the analog
ground plane with at least a 1
μ
F capacitor (Figure 3). For
single 5V operation at the highest f
CLK
of 2MHz, pin 3
should be biased at 2V. This minimizes passband gain and
phase variations.
Ratio Input Pin (10)
The DC level at this pin determines the ratio of the clock
frequency to the cutoff frequency of the filter. Pin 10 at V
+
gives a 25:1 ratio and pin 10 at V
–
gives a 50:1 ratio. For
single supply operation the ratio is 25:1 when pin 10 is at
V
+
and 50:1 when pin 10 is at ground. When pin 10 is not
tied to ground, it should be bypassed to analog ground
with a 0.1
μ
F capacitor. If the DC level at pin 10 is switched
mechanically or electrically at slew rates greater than
1V/
μ
s while the device is operating, a 10k resistor should
be connected between pin 10 and the DC source.
Analog Ground Pins (3, 5)
The filter performance depends on the quality of the
analog signal ground. For either dual or single supply
operation, an analog ground plane surrounding the pack-
Figure 2. Dual Supply Operation for an f
CLK
/f
CUTOFF
= 25:1
Figure 3. Single Supply Operation for an f
CLK
/f
CUTOFF
= 25:1
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
IN
V
+
200
V
–
V
OUT
LTC1264-7
DIGITAL SUPPLY
+
GND
CLOCK SOURCE
1264-7 F02
0.1
μ
F
0.1
μ
F
V
+
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
IN
V
+
200
V
OUT
DIGITAL SUPPLY
+
GND
CLOCK SOURCE
1264-7 F03
+
LTC1264-7
0.1
μ
F
1
μ
F
10k
10k
V
+
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