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參數(shù)資料
| 型號(hào)： | LTC1264CS |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 運(yùn)動(dòng)控制電子 |
| 英文描述： | High Speed, Quad Universal Filter Building Block |
| 中文描述： | QUAD SWITCHED CAPACITOR FILTER, BUTTERWORTH/CHEBYSHEV, UNIVERSAL, PDSO24 |
| 封裝： | 0.300 INCH, PLASTIC, SOL-24 |
| 文件頁數(shù)： | 1/12頁 |
| 文件大小： | 301K |
| 代理商： | LTC1264CS |
1
LTC1264-7
Linear Phase, Group Delay
Equalized, 8th Order
Lowpass Filter
S
FEATURE
I
Steeper Roll-Off Than Bessel Filters
I
High Speed: f
C
≤
200kHz
I
Phase Equalized Filter in a 14-Pin Package
I
Phase and Group Delay Response Fully Tested
I
Transient Response Exhibits 5% Overshoot and
No Ringing
I
65dB THD or Better Throughout a 100kHz Passband
I
No External Components Needed
D
U
ESCRIPTIO
The LTC1264-7 is a clock-tunable monolithic 8th order
lowpass filter with linear passband phase and flat group
delay. The amplitude response approximates a maximally
flat passband and exhibits steeper roll-off than an equiva-
lent 8th order Bessel filter. For instance, at twice the cutoff
frequency the filter attains 28dB attenuation (vs 12dB for
Bessel), while at three times the cutoff frequency the filter
attains 55dB attenuation (vs 30dB for Bessel). The cutoff
frequency of the LTC1264-7 is tuned via an external TTL or
CMOS clock.
The clock-to-cutoff frequency ratio of the LTC1264-7 can
be set to 25:1 (pin 10 to V
+
) or 50:1 (pin 10 to V
–
).
When the filter operates at clock-to-cutoff frequency ratio
of 25:1, the input is double-sampled to lower the risk of
aliasing.
The LTC1264-7 is optimized for speed. Depending on the
operating conditions, cutoff frequencies between 200kHz
and 250kHz can be obtained. (Please refer to the Passband
vs Clock Frequency graphs.)
The LTC1264-7 is pin-compatible with the LTC1064-X
series.
U
S
A
O
PPLICATI
I
Data Communication Filters
I
Time Delay Networks
I
Phase Matched Filters
U
A
O
PPLICATI
TYPICAL
200kHz Linear Phase Lowpass Filter
1
2
3
4
5
6
7
14
13
12
11
10
9
8
LTC1264-7
V
IN
8V
–8V
f
CLK
= 5MHz
8V
V
OUT
NOTE: THE POWER SUPPLIES SHOULD BE BYPASSED BY A
0.1
μ
F CAPACITOR CLOSE TO THE PACKAGE AND ANY PRINTED
CIRCUIT BOARD ASSEMBLY SHOULD MAINTAIN A DISTANCE
OF AT LEAST 0.2 INCHES BETWEEN ANY OUTPUT OR INPUT
PIN AND THE f
CLK
LINE.
1264-7 TA01
4-Level PAM Eye Diagram
1264-7 TA02
500ns/DIV
1
f
CLK
= 5MHz
f
C
= 200kHz
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