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參數資料
| 型號： | LTC1098LIS8#PBF |
| 廠商： | Linear Technology |
| 文件頁數： | 27/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC A/D CONV 8BIT SRL IN/OUT8SOIC |
| 標準包裝： | 100 |
| 位數： | 8 |
| 采樣率（每秒）： | 33k |
| 數據接口： | 串行 |
| 轉換器數目： | 1 |
| 功率耗散（最大）： | 780µW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 8-SOIC |
| 包裝： | 管件 |
| 輸入數目和類型： | 1 個差分，單極 |
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LTC1096/LTC1096L
LTC1098/LTC1098L
4
10968fc
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
tWHCS
CS High Time Between Data Transfer Cycles
VCC = 5V
1
μs
tWLCS
CS Low Time During Data Transfer
LTC1096, fCLK = 500kHz
LTC1098, fCLK = 500kHz
28
μs
VCC = 3V Operation
fCLK
Clock Frequency
VCC = 3V
25
250
kHz
tCYC
Total Cycle Time
LTC1096, fCLK = 250kHz
LTC1098, fCLK = 250kHz
58
μs
thDI
Hold Time, DIN After CLK↑
VCC = 3V
450
ns
tsuCS
Setup Time CS
↓ Before First CLK↑ (See Operating Sequence)
VCC = 3V, LTC1096
VCC = 3V, LTC1098
1
μs
tWAKEUP
Wake-Up Time CS
↓ Before First CLK↓ After First CLK↑
(See Figure 1 LTC1096 Operating Sequence)
VCC = 3V, LTC1096
10
μs
Wake-Up Time CS
↓ Before MSBF Bit CLK↓
(See Figure 2 LTC1098 Operating Sequence)
VCC = 3V, LTC1098
10
μs
tsuDI
Setup Time, DIN Stable Before CLK↑
VCC = 3V
1
μs
tWHCLK
CLK High Time
VCC = 3V
1.6
μs
tWLCLK
CLK Low Time
VCC = 3V
1.6
μs
tWHCS
CS High Time Between Data Transfer Cycles
VCC = 3V
2
μs
tWLCS
CS Low Time During Data Transfer
LTC1096, fCLK = 250kHz
LTC1098, fCLK = 250kHz
56
μs
LTC1096/LTC1098
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VCC
Supply Voltage
2.65
4.0
V
fCLK
Clock Frequency
VCC = 2.65V
25
250
kHz
tCYC
Total Cycle Time
LTC1096L, fCLK = 250kHz
LTC1098L, fCLK = 250kHz
58
μs
thDI
Hold Time, DIN After CLK↑
VCC = 2.65V
450
ns
tsuCS
Setup Time CS
↓ Before First CLK↑ (See Operating Sequence)
VCC = 2.65V, LTC1096L
VCC = 2.65V, LTC1098L
1
μs
tWAKEUP
Wake-Up Time CS
↓ Before First CLK↓ After First CLK↑
(See Figure 1 LTC1096L Operating Sequence)
VCC = 2.65V, LTC1096L
10
μs
Wake-Up Time CS
↓ Before MSBF Bit CLK↓
(See Figure 2 LTC1098L Operating Sequence)
VCC = 2.65V, LTC1098L
10
μs
tsuDI
Setup Time, DIN Stable Before CLK↑
VCC = 2.65V
1
μs
tWHCLK
CLK High Time
VCC = 2.65V
1.6
μs
tWLCLK
CLK Low Time
VCC = 2.65V
1.6
μs
tWHCS
CS High Time Between Data Transfer Cycles
VCC = 2.65V
2
μs
tWLCS
CS Low Time During Data Transfer
LTC1096L, fCLK = 250kHz
LTC1098L, fCLK = 250kHz
56
μs
LTC1096L/LTC1098L
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