參數(shù)資料
型號: LTC1098AIS8#PBF
廠商: LINEAR TECHNOLOGY CORP
元件分類: ADC
英文描述: 2-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8
封裝: 0.150 INCH, PLASTIC, SOIC-8
文件頁數(shù): 26/28頁
文件大?。?/td> 368K
代理商: LTC1098AIS8#PBF
7
LTC1096/LTC1096L
LTC1098/LTC1098L
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
tSMPL
Analog Input Sample Time
See Operating Sequence
1.5
CLK Cycles
fSMPL(MAX) Maximum Sampling Frequency
q
16.5
kHz
tCONV
Conversion Time
See Operating Sequence
8
CLK Cycles
tdDO
Delay Time, CLK
↓ to DOUT Data Valid
See Test Circuits (Note 9)
q
500
1000
ns
tdis
Delay Time, CS
↑ to DOUT Hi-Z
See Test Circuits (Note 9)
q
220
800
ns
ten
Delay Time, CLK
↓ to DOUT Enable
See Test Circuits (Note 9)
q
160
480
ns
thDO
Time Output Data Remains Valid After CLK
CLOAD = 100pF
400
ns
tf
DOUT Fall Time
See Test Circuits (Note 9)
q
70
250
ns
tr
DOUT Rise Time
See Test Circuits (Note 9)
q
50
150
ns
CIN
Input Capacitance
Analog Inputs On Channel
25
pF
Analog Inputs Off Channel
5
pF
Digital Input
5
pF
LTC1096/LTC1098
VCC = 3V, VREF = 2.5V, fCLK = 250kHz, unless otherwise noted.
LTC1096L/LTC1098L
VCC = 2.65V, VREF = 2.5V, fCLK = 250kHz, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
tSMPL
Analog Input Sample Time
See Operating Sequence
1.5
CLK Cycles
fSMPL(MAX) Maximum Sampling Frequency
q
16.5
kHz
tCONV
Conversion Time
See Operating Sequence
8
CLK Cycles
tdDO
Delay Time, CLK
↓ to DOUT Data Valid
See Test Circuits
q
500
1000
ns
tdis
Delay Time, CS
↑ to DOUT Hi-Z
See Test Circuits
q
220
800
ns
ten
Delay Time, CLK
↓ to DOUT Enable
See Test Circuits
q
160
480
ns
thDO
Time Output Data Remains Valid After CLK
CLOAD = 100pF
400
ns
tf
DOUT Fall Time
See Test Circuits
q
70
250
ns
tr
DOUT Rise Time
See Test Circuits
q
50
200
ns
CIN
Input Capacitance
Analog Inputs On Channel
25
pF
Analog Inputs Off Channel
5
pF
Digital Input
5
pF
The q denotes specifications which apply over the operating temperature
range.
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to GND.
Note 3: For the 8-lead PDIP, consult the factory.
Note 4: Linearity error is specified between the actual and points of the
A/D transfer curve.
Note 5: Total unadjusted error includes offset, full scale, linearity,
multiplexer and hold step errors.
Note 6: Two on-chip diodes are tied to each reference and analog input
which will conduct for reference or analog input voltages one diode drop
below GND or one diode drop above VCC. This spec allows 50mV forward
bias of either diode. This means that as long as the reference or analog
input does not exceed the supply voltage by more than 50mV, the output
code will be correct. To achieve an absolute 0V to 5V input voltage range
will therefore require a minimum supply voltage of 4.950V over initial
tolerance, temperature variations and loading. For 5.5V < VCC ≤ 9V,
reference and analog input range cannot exceed 5.55V. If reference and
analog input range are greater than 5.55V, the output code will not be
guaranteed to be correct.
Note 7: The supply voltage range for the LTC1096L/LTC1098L is from
2.65V to 4V. The supply voltage range for the LTC1096 is from 3V to 9V,
but the supply voltage range for the LTC1098 is only from 3V to 6V.
Note 8: Channel leakage current is measured after the channel selection.
Note 9: These specifications are either correlated from 5V specifications or
guaranteed by design.
AC CHARACTERISTICS
相關(guān)PDF資料
PDF描述
LTC1098CS8-3 2-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8
LTC1096IS8-3 1-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8
LTC1098ACS8-3 2-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8
LTC1098AIS8-3 2-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8
LTC1096AIS8-3 1-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8
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