參數(shù)資料
型號(hào)： LTC1098AIS8#PBF
廠(chǎng)商： LINEAR TECHNOLOGY CORP
元件分類(lèi)： ADC
英文描述： 2-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8
封裝： 0.150 INCH, PLASTIC, SOIC-8
文件頁(yè)數(shù)： 10/28頁(yè)
文件大?。?/td> 368K
代理商： LTC1098AIS8#PBF
18
LTC1096/LTC1096L
LTC1098/LTC1098L
Figure 7. LTC1098(L) “+” and “–” Input Settling Windows
CLK
DIN
DOUT
"+" INPUT
"–" INPUT
SAMPLE
HOLD
"+" INPUT MUST
SETTLE DURING
THIS TIME
tSMPL
tCONV
CS
SGL/DIFF
START
MSBF
DON'T CARE
1ST BIT TEST "–" INPUT MUST
SETTLE DURING THIS TIME
B7
LTC1096/8 F07
U
S
A
O
PPLICATI
WU
U
I FOR ATIO
(Figure 6) and connect the center point to the MPU input.
It should be noted that to get full shutdown, the CS input
of the LTC1096/LTC1098 must be driven to the VCC
voltage. This would require adding a level shift circuit to
the CS signal in Figure 6.
+IN
–IN
GND
VCC
CLK
DOUT
VREF
50k
6V
4.7
F
MPU
(e.g. 8051)
5V
P1.4
P1.3
P1.2
LTC1096/98 F06
DIFFERENTIAL INPUTS
COMMON MODE RANGE
0V TO 6V
9V
LTC1096
9V
OPTIONAL
LEVEL SHIFT
CS
Figure 6. Interfacing a 9V Powered LTC1096 to a 5V System
BOARD LAYOUT CONSIDERATIONS
Grounding and Bypassing
The LTC1096(L)/LTC1098(L) should be used with an ana-
log ground plane and single point grounding techniques.
The GND pin should be tied directly to the ground plane.
The VCC pin should be bypassed to the ground plane with
a 1
F tantalum with leads as short as possible. If power
supply is clean, the LTC1096(L)/LTC1098(L) can also
operate with smaller 0.1
F surface mount or ceramic
bypass capacitors. All analog inputs should be referenced
directly to the single point ground. Digital inputs and
outputs should be shielded from and/or routed away from
the reference and analog circuitry.
SAMPLE-AND-HOLD
Both the LTC1096(L) and the LTC1098(L) provide a built-
in sample-and-hold (S&H) function to acquire signals.
The S&H of the LTC1096(L) acquires input signals from
“+” input relative to “–” input during the tWAKEUP time (see
Figure 1). However, the S&H of the LTC1098(L) can
sample input signals in the single-ended mode or in the
differential inputs during the tSMPL time (see Figure 7).
Single-Ended Inputs
The sample-and-hold of the LTC1098(L) allows conver-
sion of rapidly varying signals. The input voltage is sampled
during the tSMPL time as shown in Figure 7. The sampling
interval begins as the bit preceding the MSBF bit is shifted
相關(guān)PDF資料
PDF描述
LTC1098CS8-3 2-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8
LTC1096IS8-3 1-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8
LTC1098ACS8-3 2-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8
LTC1098AIS8-3 2-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8
LTC1096AIS8-3 1-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8
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