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參數(shù)資料
| 型號： | LTC1065ISW#TR |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 15/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FILTER LP 5TH ORD LIN 16SOIC |
| 標準包裝： | 1,000 |
| 濾波器類型： | 貝塞爾，低通開關電容器 |
| 頻率 - 截止或中心： | 50kHz |
| 濾波器數(shù)： | 1 |
| 濾波器階數(shù)： | 5th |
| 電源電壓： | ±2.37 V ~ 8 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.295"，7.50mm 寬） |
| 供應商設備封裝： | 16-SOIC |
| 包裝： | 帶卷 (TR) |
8
LTC1065
1065fb
INTERNAL CLOCK FREQUENCY (kHz)
K
1.25
1.20
1.15
1.10
1.05
1.00
0.95
0.90
0.85
0.80
0.75
1065 F04b
100
300
500
VS = ±7.5V
VS = ±2.5V
fCLK = K/RC
C = 200pF
TA = 25°C
VS = ±5V
200
400
VIN
R
VOUT
1065 F04a
C
V–
V+
1
2
3
4
8
7
6
5
LTC1065
V–
50k
V+
0.1
F
VOUT
1065 F03
0.1
F
CLOCK IN
–
+
LT1022
20pF
VIN
50k
8
7
6
5
1
2
3
4
LTC1065
TEST CIRCUIT
Figure 3. Test Circuit for THD
Self-Clocking Operation
The LTC1065 features an internal oscillator which can be
tuned via an external RC. The LTC1065’s internal oscillator
is primarily intended for generation of clock frequencies
below 500kHz. The first curve of the Typical Performance
Characteristics section shows how to quickly choose the
value of the RC for a given frequency. More precisely, the
frequency of the internal oscillator is equal to:
fCLK = K/RC
For clock frequencies (fCLK) below 100kHz, K equals 1.07.
Figure 4b shows the variation of the parameter K versus
clock frequency and power supply. First choose the de-
sired clock frequency (fCLK< 500kHz), then through Figure
4b pick the right value of K, set C = 200pF and solve for R.
Example 1: fCUTOFF = 2kHz, fCLK = 200kHz, VS = ±5V,
TA = 25°C, K = 1.0, C = 200pF
then,
R = (1.0)/(200kHz
× 204pF) = 24.5k.
U
S
A
O
PPLICATI
WU
U
I FOR ATIO
Figure 4a.
Figure 4b. fCLK vs K
Note a 4pF parasitic capacitance is assumed in parallel
with the external 200pF timing capacitor. Figure 5 shows
the clock frequency variation from – 40
°C to 85°C. The
200kHz clock of Example 1 will change by –1.75% at 85
°C.
For a limited temperature range, the internal oscillator of
the LTC1065 can be used to generate clock frequencies
above 500kHz (Figures 6 and 7). The data of Figure 6 is
derived from several devices. For a given external (RC)
value, the observed device-to-device clock frequency varia-
tion was
±1% (VS = ±5V), and ±1.25% for VS = ±2.5V.
Example 2:
fCUTOFF = 20kHz, fCLK = 2MHz, VS = ±7.5V,
TA = 25°C, C = 10pF
from Figure 6, K = 0.575,
and,
R = (0.575)/(2MHz
× 14pF) = 20.5k.
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